UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 587

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4 IDLE Mode
15.4.1 Setting and operation status
mode.
peripheral functions stops.
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with an external clock continue operating.
the on-chip peripheral functions. The clock generator and PLL do not stop, so the normal operation mode can be
restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same
manner as when the HALT mode is released.
15.4.2 Releasing IDLE mode
unmasked internal interrupt request signal (INTLVI), unmasked internal interrupt request signal from the peripheral
functions operable in the IDLE mode (interrupt request signal related to CSIB in the slave mode), or reset signal
(RESET pin input, reset signal generation by low-voltage detection (LVIRES), and reset signal generation by power-
on clear (POCRES)).
Unmasked maskable interrupt request
The IDLE mode is set by clearing (0) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation
In the IDLE mode, the clock generator and PLL continue operation but clock supply to the CPU and other on-chip
As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are
Table 15-5 shows the operation status in the IDLE mode.
The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The IDLE mode is released by an unmasked external interrupt request signal (INTP0 to INTP5 pin input),
After the IDLE mode has been released, the normal operation mode is restored.
(1) Releasing IDLE mode by unmasked maskable interrupt request signal
The IDLE mode is released by an unmasked maskable interrupt request signal, regardless of the priority of the
interrupt request. If the IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is
issued later is processed as follows.
Caution When the PSC.INTM bit is set to 1, the IDLE mode cannot be released by an unmasked
(a) If an interrupt request signal with a priority lower than or same as the interrupt currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt currently being serviced is
generated, the IDLE mode is released, but the newly generated interrupt request signal is not
acknowledged. The interrupt request signal itself is retained. Therefore, execution starts at the next
instruction after the IDLE instruction.
issued, the IDLE mode is released and that interrupt request signal is acknowledged. Therefore, the
execution branches to the handler address.
Release Source
set the IDLE mode.
Table 15-4. Operation After Releasing IDLE Mode by Interrupt Request Signal
maskable interrupt request signal.
Execution branches to the handler
address or the next instruction is
executed
CHAPTER 15 STANDBY FUNCTION
User’s Manual U17716EJ2V0UD
Interrupt Enabled (EI) Status
The next instruction is executed
Interrupt Disabled (DI) Status
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