UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 410

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

408
[TMQ1 operation]
<Q1> Write the TQ1CCR1 register.
<Q2> Rewrite the register at the transfer timing that is generated after the TQ1CCR1 register has been rewritten.
<Q3> The registers are transferred all at once at the transfer timing.
<Q4> The transfer timing is also culled as the interrupts are culled.
[TMP1 operation]
<P1> Write the TQ1CCR1 register.
<P2> Rewrite the register at the transfer timing that is generated after the TQ1CCR1 register has been rewritten.
<P3> The registers are transferred all at once at the transfer timing.
<P4> The transfer timing is also culled as the interrupts are culled.
Remark
INTTQ1CC0 signal
This is an example of the operation when the TQ1OPT1.TQ1ICE bit = 1, TQ1OPT1.TQ1IOE bit = 1,
TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits = 00001.
INTTQ1OV signal
16-bit counter
16-bit counter
CCR0 buffer
CCR1 buffer
CCR2 buffer
CCR3 buffer
CCR0 buffer
CCR1 buffer
OPT1 buffer
TQ1CCR0
TQ1CCR1
TQ1CCR2
TQ1CCR3
Transfer
TQ1OPT1
TP1CCR0
TP1CCR1
Figure 9-31. Basic Operation in Intermittent Batch Rewrite Mode
Transfer
(TMQ1)
(TMP1)
register
register
register
register
register
register
register
register
register
register
register
register
register
register
timing
timing
CHAPTER 9 MOTOR CONTROL FUNCTION
<Q1>&<P1>
User’s Manual U17716EJ2V0UD
<Q4>
<Q4>
<P4>
<Q2>
<P2>
<Q3>
<Q3>
<Q3>
<Q3>
<Q3>
<P3>
<P3>
<Q4>
<Q4>
<P4>