UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 220

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UPD70F3713GC-8BS-A

Manufacturer Part Number
UPD70F3713GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3713GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3713GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
218
TPnCTL0
TPnCTL1
TPmIOC0
TPkIOC1
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
(c) TMPm I/O control register 0 (TPmIOC0)
(d) TMPk I/O control register 1 (TPkIOC1)
Note The setting is invalid when the TPkCTL1.TPkEEE bit = 1.
Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
TP1SYE
TPnCE
0/1
0
0
0
TPmEST
Figure 6-38. Register Setting in Free-Running Timer Mode (1/2)
0
0
0
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
TPkEEE
0/1
0
0
0
0
0
0
0
User’s Manual U17716EJ2V0UD
TPmOL1
TPkIS3
0/1
0/1
0
0
TPnCKS2 TPnCKS1 TPnCKS0
TPnMD2 TPnMD1 TPnMD0
TPmOE1 TP0OL0
TPkIS2
0/1
0/1
0/1
1
TPkIS1
0/1
0/1
0/1
0
TP0OE0
TPkIS0
0/1
0/1
0/1
1
Select valid edge
of TIPk0 pin input
Select valid edge
of TIPk1 pin input
1, 0, 1:
Free-running timer mode
Select count clock
0: Stop counting
1: Enable counting
0: Operate with count
1: Count on external
0: Disable TOP00 pin output
1: Enable TOP00 pin output
Setting of TOP00 pin output level
before count operation
0: Low level
1: High level
0: Disable TOPm1 pin output
1: Enable TOPm1 pin output
Setting of TOPm1 pin output level
before count operation
0: Low level
1: High level
clock selected by
TPkCKS0 to TPkCKS2 bits
event count input signal
Note
Note

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