UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 705

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
22.3.3 Reset operation by low-voltage detector
system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status.
detection voltage.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator
Peripheral clock (f
Internal system clock (f
CPU clock (f
CPU
Watchdog timer 2
Internal RAM
I/O lines (ports/alternate-function
pins)
On-chip peripheral I/O register
LVI
On-chip peripheral functions other
than above
If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a
The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI
The main clock oscillator is stopped during the reset period.
When the LVIMD bit = 0, an interrupt request signal (INTLVI) is generated if a low voltage is detected.
Remark
CPU
For the reset timing of the low-voltage detector, see CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI).
)
Item
X
to f
XT
Table 22-3. Hardware Status During Reset Operation by Low-Voltage Detector
X
)
X
)
XX
/1,024)
),
Oscillation stops
Oscillation continues
Oscillation stops
Operation stops
Operation stops
Initialized
Operation stops (initialized to 0)
Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
High impedance
Initialized to specified status, OCDM register retains its value.
Operation stops
Operation stops
During Reset
Oscillation starts
Oscillation starts
Operation starts after securing oscillation
stabilization time
Operation starts after securing oscillation
stabilization time (initialized to f
Program execution starts after securing
oscillation stabilization time
Counts up from 0 with internal oscillation
clock as source clock.
Operation can be started after securing
oscillation stabilization time.
CHAPTER 22 RESET FUNCTIONS
After Reset
XX
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