UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 689

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
21.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode
21.7.1 Setting and operation status
subclock operation mode is set by setting the REGOVL0 register to 02H in the subclock operation mode.
Check whether the clock has been switched by using the PCC.CLS bit.
operates only on the subclock.
because the subclock is used as the internal system clock. In addition, power consumption can be further reduced to the
level of the STOP mode by stopping the operation of the main clock oscillator. Power consumption decreases further in
the low-voltage subclock operation mode because the voltage of the regulator is lowered.
external clock continuing to operate, but stop supply of the external clock input to CSIBn and UARTA0 in the low-voltage
subclock operation mode (n = 0 to 2).
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. The low-voltage
When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system
In the subclock operation mode, power consumption can be reduced to a level lower than in the normal operation mode
When the main clock oscillator is stopped in the subclock operation mode, CSIBn and UARTA0 can operate with the
Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits
Remark Internal system clock (f
Be sure to set the low-voltage subclock operation mode in the following procedure.
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are
(using a bit manipulation instruction to manipulate the bit is recommended). For details of the
PCC register, see 6.3 (1) Processor clock control register (PCC).
satisfied and set the subclock operation mode.
Internal system clock (f
CLK
): Clock generated from main clock (f
CK2 to CK0 bits
CLK
) > Subclock (f
XT
= 32.768 kHz) × 4
CHAPTER 21 STANDBY FUNCTION
XX
) in accordance with the settings of the
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