UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 18

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Internal
memory
Memory
space
External bus interface
General-purpose register
Clock
I/O port
Timer
Real-time output port
10-bit A/D converter
8-bit D/A converter
Serial interface
DMA controller
Interrupt source
Power save function
Reset source
CRC function
On-chip debug
Operating power supply voltage
Operating ambient temperature
Package
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
Main clock
(oscillation frequency)
Subclock
(oscillation frequency)
Internal oscillator
Minimum instruction
execution time
DSP function
16-bit TMP
16-bit TMQ
16-bit TMM
Watch timer
WDT
Generic Name
Part Number
Flash memory
RAM
Logical space
External memory area
External
Internal
CSIB:
MINICUBE
2.2 to 3.6 V @5 MHz, 2.7 to 3.6 V @20 MHz
Address bus: 18
Address data bus: 16
Multiplexed bus mode output supported
32 bits × 32 registers
Ceramic/crystal
(in PLL mode: f
External clock
(in PLL mode: f
Crystal (f
f
50 ns (main clock (f
32 × 32 = 64: 200 to 250 ns (at 20 MHz)
32 × 32 + 32 = 32: 300 ns (at 20 MHz)
16 × 16 = 32: 50 to 100 ns (at 20 MHz)
16 × 16 + 32 = 32: 150 ns (at 20 MHz)
I/O: 66 (5 V tolerant/N-ch open-drain output
selectable: 25)
UARTA:
CSIB/I
UARTA/I
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE/
low-voltage STOP/low-voltage subclock/low-voltage sub-IDLE mode
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
16-bit error detection code generated for 8-bit unit data
−40 to +85°C
80-pin LQFP (12 × 12 mm)
80-pin LQFP (14 × 14 mm)
R
= 220 kHz (TYP.)
μ
4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
PD70F3735
2
128 KB
C bus:
Table 1-1. V850ES/Jx3-L Product List
8 KB
2
XT
C bus: 1 channel
®
= 32.768 kHz)
, MINICUBE2 supported
X
X
V850ES/JF3-L
2 channels
2 channels
1 channel
= 2.5 to 5 MHz (multiplied by 4), in clock through mode: f
= 2.5 to 5 MHz (multiplied by 4), in clock through mode: f
4 channels
4 bits × 1 channel, 2 bits × 1 channel, or 6 bits × 1 channel
8 channels
1 channel
1 channel
1 channel
1 channel
1 channel
9 (9)
XX
40
) = 20 MHz)
Note
μ
PD70F3736
256 KB
16 KB
64 MB
15 MB
Address bus: 22
Address data bus: 16
Separate bus/multiplexed bus mode selectable
I/O: 84 (5 V tolerant/N-ch open-drain output
selectable: 31)
CSIB:
UARTA/CSIB:
CSIB/I
UARTA/I
100-pin LQFP (14 × 14 mm)
100-pin LQFP (14 × 20 mm)
μ
PD70F3737
2
128 KB
C bus:
8 KB
2
C bus: 2 channels
CHAPTER 1 INTRODUCTION
V850ES/JG3-L
12 channels
3 channels
1 channel
1 channel
6 channels
2 channels
1 channel
1 channel
1 channel
1 channel
9 (9)
48
Note
X
X
= 2.5 to 10 MHz)
= 2.5 to 5 MHz)
μ
PD70F3738
256 KB
16 KB
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