UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 514

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing
INTCBnT signal
CBnTSF bit
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous transfer
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device
(5) When a serial clock is input, output the transmit data from the SOBn pin in synchronization with the serial
(6) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to
(7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal is
(8) When a serial clock is input following completion of the transmission of the transfer data length set with the
(9) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to
(10) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the
(11) To release the transmission enable status, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE
Caution In continuous transmission mode, the reception completion interrupt request signal
Remark
SCKBn pin
SOBn pin
external clock (SCKBn), and slave mode.
mode at the same time as enabling the operation of the communication clock (f
waits for a serial clock input.
clock.
the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is generated.
generated.
CBnCTL2 register, continuous transmission is started.
the CBnTX register is enabled, the INTCBnT signal is generated. To end continuous transmission with the
current transmission, do not write to the CBnTX register.
CBnTX register, clear the CBnTSF bit to 0 to end transmission.
bit = 0 after checking that the CBnTSF bit = 0.
(1)
(2)
(3)
(INTCBnR) is not generated.
n = 0 to 2
(4)
(5)
Bit 7
(6)
Bit 6
Bit 5
Bit 4 Bit 3
(7)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 2
Bit 1
Bit 0
(8)
Bit 7
(9)
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
CCLK
(10)
Bit 0
).
(11)
Page 498 of 816
CCLK
) =