UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 173

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Note This idle state (TI) does not depend on the BCC register settings.
Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode.
Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded.
AD15 to AD0
A17, A16
CLKOUT
AD15 to AD0
HLDRQ
HLDAK
ASTB
CLKOUT
A17, A16
RD
2. The broken lines indicate high impedance.
2. TAHW (address hold wait): Image of low-level width of T1 state expanded.
3. The broken lines indicate high impedance.
ASTB
WAIT
RD
Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
Figure 5-9. Address Wait Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1
T1
A1
T2
A1
D1
A1
T2
D1
T3
Undefined
Undefined
TI
Note
AD15 to AD0
A17, A16
CLKOUT
TH
ASTB
WAIT
RD
TH
TASW
TH
CHAPTER 5 BUS CONTROL FUNCTION
TH
T1
A1
Undefined
Undefined
TI
A1
Note
TAHW
A2
T1
T2
D1
D2
T2
A2
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T3