UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 681

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UPD70F3735GC-GAD-AX

Manufacturer Part Number
UPD70F3735GC-GAD-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GC-GAD-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
21.5.3 Securing setup time when releasing IDLE2 mode
than the main clock oscillator stops after the IDLE2 mode is set.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request
(2) Release by reset (RESET pin input, WDT2RES generation)
Oscillated waveform
IDLE mode status
signal
Secure the specified setup time by setting the OSTS register.
When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS
register setting. When it overflows, the normal operation mode is restored.
Interrupt request
This operation is the same as that of a normal reset.
The oscillation stabilization time differs depending on the option byte setting. For details, see CHAPTER 27
OPTION BYTE.
Main clock
ROM circuit stopped
Setup time count
CHAPTER 21 STANDBY FUNCTION
Page 665 of 816

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