UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 687

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
21.6.3 Re-setting after release of low-voltage STOP mode
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(1) If low-voltage STOP mode is released by interrupt
(2) If low-voltage STOP mode is released by reset
The status after the low-voltage STOP mode has been released is as follows.
• Regulator: Automatically returns to the normal level.
• REGOVL0 register = 01H (low-voltage STOP mode): Value described in 21.6.1 (1) <5> is retained.
• REGPR register = 00H (protection data): Value described in 21.6.1 (1) <6> is retained.
(a) To continuously use the REGOVL0 register = 01H (low-voltage STOP mode), the other registers do not have to
(b) Follow this procedure when returning the REGOVL0 register = 00H.
The CPU transits to the normal operation mode after it has been released from the reset status, and the REGOVL0
register is initialized to 00H and the REGPR register to 00H (protection data). Be sure by setting an option byte to
secure the time necessary for setting up the regulator. For details, see CHAPTER 27 OPTION BYTE.
Caution The interrupt requests that are set to 1 (disabled) by the PSC.NMI1M, PSC.NMI0M, and
It is necessary to secure the recovery time within the oscillation stabilization time (set value of the OSTS register).
Be sure to secure by using the OSTS register the time for the regulator to recover from low-voltage mode + PLL
setup time + main oscillator stabilization time.
Be sure to observe the above sequence.
be set again.
<1> Disable the DMA.
<2> • Disable the maskable interrupt by the DI instruction.
<3> Write C9H (enabling data) to the REGPR register.
<4> Write 00H to the REGOVL0 register.
<5> Write 00H (protection data) to the REGPR register.
<6> As necessary, enable the maskable interrupt, NMI interrupt, or INTWDT2 interrupt by enabling DMA or
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (stop watchdog timer 2 or set a mode
the EI instruction (restore the settings <1> and <2> above).
PSC.INTM bits are disabled, and the low-voltage STOP mode is not released.
other than the INTWDT2 mode. Create a status in which the INTWDT2 signal is not generated
immediately after watchdog timer 2 has been cleared).
CHAPTER 21 STANDBY FUNCTION
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