UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 566

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UPD78F0513AGB-GAF-AX

Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet

Specifications of UPD78F0513AGB-GAF-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
UPD78F0513AGB-GAF-AX
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Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(5) IIC function expansion register 0 (IICX0)
(6) I
This register sets the function expansion of I
IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1,
and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 18.3 (6) I
method).
Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears IICX0 to 00H.
The I
For example, the I
ns is calculated using following expression.
2
C transfer clock setting method
Address: FFA9H
2
f
f
C transfer clock frequency (f
SCL
SCL
Symbol
IICX0
m = 12, 18, 24, 44, 66, 86 (see Table 18-2 Selection Clock Setting)
T:
t
t
= 1/(m × T + t
R
F
= 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 48.1 kHz
:
:
1/f
SCL0 rise time
SCL0 fall time
SCL0
W
2
SCL0
C transfer clock frequency (f
Figure 18-9. Format of IIC Function Expansion Register 0 (IICX0)
7
0
After reset: 00H
R
inversion
+ t
F
t
R
)
6
0
SCL
) is calculated using the following expression.
m/2
5
0
R/W
2
T
C.
m
SCL
SCL0
T + t
) when f
4
0
inversion
R
+ t
F
W
t
F
= f
PRS
3
0
m/2
/2 = 4.19 MHz, m = 86, t
CHAPTER 18 SERIAL INTERFACE IIC0
T
SCL0
2
0
inversion
1
0
2
C transfer clock setting
R
= 200 ns, and t
CLX0
<0>
F
= 50
566

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