UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 308
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
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Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
This is an application example where the pulse width of the signal input to the TI00n pin is measured.
By setting CRC0n, the count value can be captured to CR00n in the phase reverse to the falling edge of the TI00n pin
(i.e., rising edge) and to CR01n at the falling edge of the TI00n pin.
The high- and low-level widths of the input pulse can be calculated by the following expressions.
• High-level width = [CR01n value] – [CR00n value] × [Count clock cycle]
• Low-level width = [CR00n value] × [Count clock cycle]
If the reverse phase of the TI00n pin is selected as a trigger to capture the count value to CR00n, the INTTM00n
signal is not generated. Read the values of CR00n and CR01n to measure the pulse width immediately after the
INTTM01n signal is generated.
However, if the valid edge specified by bits 6 and 5 (ES1n1 and ES1n0) of prescaler mode register 0n (PRM0n) is
input to the TI01n pin, the count value is not captured but the INTTM00n signal is generated. To measure the pulse
width of the TI00n pin, mask the INTTM00n signal when it is not used.
Remark n = 0:
Capture & count clear input
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
(TMC0n3, TMC0n2)
Capture interrupt
Capture interrupt
(TI00n pin input)
Capture register
Capture register
TM0n register
Operable bits
Capture input
(INTTM01n)
(INTTM00n)
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
(CR00n: Capture Register, CR01n: Capture Register) (3/3)
(CR00n)
(CR01n)
(TI01n)
0000H
(c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH
L
L
00
0000H
0000H
L
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
M
L
10
N
M
P
O
N
O
Q
P
R
Q
S
R
T
S
T
W
W
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