UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 558
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
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SEMIKRON
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Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1. This flag’s signal is invalid when IICE0 = 0.
ACKE0
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• Reset
Condition for clearing (SPIE0 = 0)
• Cleared by instruction
• Reset
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling
edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the
falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• Reset
WTIM0
SPIE0
0
1
0
1
0
1
2. The set value is invalid during address transfer and if the code is not an extension code.
Notes 1, 2
Note 1
Note 1
When the device serves as a slave and the addresses match, an acknowledge is generated regardless of the
set value.
Disable
Enable
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (2/4)
Enable/disable generation of interrupt request when stop condition is detected
Control of wait and interrupt request generation
Acknowledgment control
Condition for setting (SPIE0 = 1)
• Set by instruction
Condition for setting (WTIM0 = 1)
• Set by instruction
Condition for setting (ACKE0 = 1)
• Set by instruction
CHAPTER 18 SERIAL INTERFACE IIC0
558
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