UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 407
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
21
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(2) Port mode register 14 (PM14)
Notes 2.
Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
Remarks 1. f
This register sets port 14 input/output in 1-bit units.
When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUSY0/BUZ pin for buzzer output,
clear PM140 and PM141 and the output latches of P140 and P141 to 0.
PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM14 to FFH.
3.
Remark
2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
2. f
If the peripheral hardware clock (f
when 1.8 V ≤ V
prohibited.
The PCL output clock prohibits settings if they exceed 10 MHz.
Address: FF2EH
Symbol
PM14
PRS
SUB
: Peripheral hardware clock frequency
: Subsystem clock frequency
The figure shown above presents the format of port mode register 14 of 78K0/KF2 products. For
the format of port mode register 14 of other products, see (1) Port mode registers (PMxx) in 5.3
Registers Controlling Port Function.
PM14n
7
1
0
1
DD
Figure 12-5. Format of Port Mode Register 14 (PM14)
< 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: f
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
6
1
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
PM145
PRS
5
P14n pin I/O mode selection (n = 0 to 5)
) operates on the internal high-speed oscillation clock (XSEL = 0)
R/W
PM144
4
PM143
3
PM142
2
PM141
1
PM140
0
PRS
) is
407
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