UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 260
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
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Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
Caution
(3) CPU operating with subsystem clock (D) after reset release (A)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(A) → (B)
Status Transition
(A) → (B) → (C) (X1 clock: 1 MHz ≤ f
10 MHz)
(A) → (B) → (C) (external main clock: 1 MHz ≤
f
(A) → (B) → (C) (X1 clock: 10 MHz < f
20 MHz)
(A) → (B) → (C) (external main clock: 10 MHz <
f
(A) → (B) → (D) (XT1 clock)
(A) → (B) → (D) (external subsystem clock)
Status Transition
XH
XH
Table 6-6 shows transition of the CPU clock and examples of setting the SFR registers.
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
≤ 10 MHz)
≤ 20 MHz)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
Note The 78K0/KB2 is not provided with a subsystem clock.
Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL
SPECIFICATIONS ((A2) GRADE PRODUCTS: T
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Status Transition
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
Setting Flag of SFR Register
Setting Flag of SFR Register
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (1/5)
XH
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
XH
≤
≤
SFR registers do not have to be set (default status after reset release).
AMPH
XTSTART
0
0
1
1
0
1
0
EXCLK
A
0
1
0
1
= −40 to +125°C)).
EXCLKS
0
×
1
OSCSEL
1
1
1
1
Note
SFR Register Setting
OSCSELS
MSTOP
CHAPTER 6 CLOCK GENERATOR
0
0
0
0
1
×
1
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Oscillation
Necessary
XSEL
1
1
1
1
CSS
MCM0
1
1
1
1
1
1
260
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