UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 296
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
21
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
(c) 16-bit timer output control register 0n (TOC0n)
(d) Prescaler mode register 0n (PRM0n)
Remark n = 0:
ES1n1
0
0
0
0
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
OSPT0n
ES1n0
0
0
Figure 7-25. Example of Register Settings in External Event Counter Mode (1/2)
0
0
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
OSPE0n
ES0n1
0
0/1
0
0
TOC0n4
ES0n0
0
0
0/1
0/1
TMC0n3 TMC0n2 TMC0n1
LVS0n
1
0
0/1
3
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
CRC0n2 CRC0n1 CRC0n0
LVR0n
1
0
0/1
2
0
PRM0n1 PRM0n0
TOC0n1
0
0
0/1
1
OVF0n
0
0
TOE0n
0/1
1
Clears and starts on match
between TM0n and CR00n.
CR00n used as
compare register
Selects count clock
(specifies valid edge of TI00n).
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
0: Disables TO0n output
1: Enables TO0n output
Specifies initial value of
TO0n output F/F
00: Does not invert TO0n output on match
01: Inverts TO0n output on match between
10: Inverts TO0n output on match between
11: Inverts TO0n output on match between
between TM0n and CR00n/CR01n.
TM0n and CR00n.
TM0n and CR01n.
TM0n and CR00n/CR01n.
296
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