UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 445
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
21
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 445 of 982
- Download datasheet (7Mb)
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
1. Stop bit length: 1
2. Stop bit length: 2
(c) Transmission
If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0)
of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to
transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data.
When transmission is started, the start bit is output from the T
the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set
by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as
soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
T
T
X
X
D0 (output)
D0 (output)
INTST0
INTST0
transmission completion interrupt signal (INTST0) is generated.
Figure 14-8. Transmission Completion Interrupt Request Timing
Start
Start
D0
D0
D1
D1
D2
D2
CHAPTER 14 SERIAL INTERFACE UART0
X
D0 pin, and the transmit data is output followed by
D6
D6
D7
D7
Parity
Parity
Stop
Stop
445
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