MC56F8366MFVE Freescale Semiconductor, MC56F8366MFVE Datasheet - Page 40

• Manufacturer Part Number: MC56F8366MFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8366MFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 544KB (272K x 16)
• Program Memory Type: FLASH
• Ram Size: 18K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2.3
The recommended method of connecting an external clock is given in
source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an
external clock source as well.
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions without the internal Relaxation Oscillator, since the 56F8366/56F8166 devices do
NOT contain this oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8366 and 56F8166 devices are 16-bit motor-control chip based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
On-chip memory sizes for each device are summarized in
identified in the “Use Restrictions” column of
40
•
•
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
External Clock Source
Figure 3-4 Connecting an External Clock Register
External
XTAL
Clock
56F8366 Technical Data, Rev. 7
EXTAL
V
SS
Table
Note: When using an external clocking source
with this configuration, the input “CLKMODE”
should be high and the COHL bit in the OSCTL
register should be set to 1.
4-1.
Table
4-1. Flash memories’ restrictions are
Figure
3-4. The external clock
Freescale Semiconductor
Preliminary