MC56F8366MFVE Freescale Semiconductor, MC56F8366MFVE Datasheet - Page 131

• Manufacturer Part Number: MC56F8366MFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8366MFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 544KB (272K x 16)
• Program Memory Type: FLASH
• Ram Size: 18K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
Note:
6.5.10.1
This field represents the upper two address bits of the “hard coded” I/O short address.
6.5.10.2
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.5.11
The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a
power-saving feaure. The clocks can be individually controller for each peripheral on the chip.
6.5.11.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Freescale Semiconductor
Preliminary
Base + $D
Base + $E
Base + $D
RESET
RESET
RESET
Write
Write
Write
Read
Read
Read
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is three cycles.
Peripheral Clock Enable Register 2 (SIM_PCE2)
Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
Reserved—Bits 15–1
Figure 6-15 I/O Short Address Location High Register (SIM_ISALH)
Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL)
15
15
15
1
1
1
0
0
14
14
14
1
1
1
0
0
13
13
13
1
1
1
0
0
12
12
12
1
1
1
0
0
11
11
11
56F8366 Technical Data, Rev. 7
1
1
1
0
0
10
10
10
1
1
1
0
0
9
1
1
9
1
9
0
0
8
8
8
1
1
1
0
0
ISAL[21:6]
7
7
7
1
1
1
0
0
6
6
6
1
1
1
0
0
5
5
5
1
1
1
0
0
4
4
4
1
1
1
0
0
3
3
3
1
1
1
0
0
2
2
2
1
1
1
0
0
Register Descriptions
ISAL[23:22]
1
1
1
1
1
0
0
CAN
0
0
0
1
1
2
1
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