MC56F8366MFVE Freescale Semiconductor, MC56F8366MFVE Datasheet
MC56F8366MFVE
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MC56F8366MFVE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8366 Rev. 7 11/2009 freescale.com ...
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... Calibration Factors to be viewed as worst case 56F8366 Technical Data, Rev. 7 Table 10-1; also removed overall Table Table 13-1. Table Table 2-2. Clarified external reference Table 2-2. Table 2-2: Table 2- the design used in a debugging SS Table 2-2. Freescale Semiconductor 10-4. 10-4. Preliminary ...
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... FlexCAN SPI0 or SCI1 or GPIOE GPIOD 4 56F8366/56F8166 Block Diagram - 144 LQFP Freescale Semiconductor Preliminary • Temperature Sensor • two Quadrature Decoders • Optional On-Chip Regulator • two FlexCAN modules • Two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interfaces (SPIs) • four General Purpose Quad Timers • ...
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... Thermal Design Considerations . . . . . . . . 178 12.2. Electrical Design Considerations . . . . . . . 179 12.3. Power Distribution and I/O Ring Part 13: Ordering Information . . . . . . . . . 181 56F8366 Technical Data, Rev. 7 Interrupt Timing . . . . . . . . . . . . . . 156 Timing . . . . . . . . . . . . . . . . . . . . . 159 Timing . . . . . . . . . . . . . . . . . . . . . 163 Parameters . . . . . . . . . . . . . . . . . 166 Information . . . . . . . . . . . . . . . . . . 171 Information . . . . . . . . . . . . . . . . . 174 Implementation . . . . . . . . . . . . . . 180 Freescale Semiconductor Preliminary ...
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... Table 1-1 outlines the key differences between the 56F8366 and 56F8166 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor Dedicated GPIO Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8366 60MHz/60 MIPS 4KB 8KB — ...
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... Timer D with two pins — In the 56F8166, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO • Optional On-Chip Regulator • two FlexCAN (CAN Version 2.0 B-compliant ) modules with 2-pin port for transmit and receive 6 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... The 56F8366 and 56F8166 support program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provides two external dedicated interrupt lines and General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 7 Device Description ...
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... Data RAM. It also supports program execution from external memory. A total of 32KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory area, which can be independently 8 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 7 Award-Winning Development Environment ...
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... The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 10 Figure 1-1 and Figure 56F8366 Technical Data, Rev. 7 1-2. Figure 1-1 illustrates how the Part 2, Signal/Connection Freescale Semiconductor Preliminary ...
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... I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. Freescale Semiconductor Preliminary pdb_m[15:0] pab[20:0] cdbw[31:0] ...
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... Figure 1-2 Peripheral Subsystem 56F8366 Technical Data, Rev. 7 Interrupt Controller Low Voltage Interrupt POR & LVI System POR RESET SIM COP Reset COP 2 FlexCAN 2 FlexCAN2 12 PWMA 13 PWMB ch2i 1 Timer C ch2o 8 ADCB 8 ADCA 1 TEMP_SENSE , V V REFH REFP, REFMID , and V pins. REFLO Freescale Semiconductor , Preliminary ...
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... Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. Freescale Semiconductor Preliminary Table 1-2 Bus Signal Names Function ...
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... Details any chip issues that might be present Logic State True False True False 56F8366 Technical Data, Rev. 7 Centers, or online Order Number DSP56800ERM MC56F8300UM MC56F83xxBLUM MC56F8366 MC56F8366E MC56F8166E Signal State 1 Voltage Asserted Deasserted Asserted Deasserted Freescale Semiconductor Preliminary at ...
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... Temperature Sense Dedicated GPIO 1. If the on-chip regulator is disabled, the V 2. Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO Freescale Semiconductor Preliminary Figure 2-1. In Table 2-2, each table row describes the signal or signals pins serve as 2 ...
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... Quadrature Decoder 0 or Quad Timer A or GPIO SPI0 or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA or GPIO PWMB or GPIO ADCA REF ADCB Temperature Sensor FlexCAN QUAD TIMER C and D or GPIO INTERRUPT/ PROGRAM CONTROL 1 (144-pin LQFP) Freescale Semiconductor Preliminary ...
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... RXD0 (GPIOE1) TXD1 (GPIOD6) SCI 1 RXD1 (GPIOD7) or GPIO JTAG/ EOnCE Port Figure 2-2 56F8166 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary V DD_IO 7 PHASEA0 (TA0, GPIOC4 PHASEB0 (TA1, GPIOC5) 1 INDEX0 (TA2, GPIOC6) ...
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... Oscillator and PLL Power — This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. V — These pins provide ground for chip logic and I/O drivers. SS 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... PP CLKMODE 87 Input EXTAL 82 Input XTAL 81 Input/ Output Freescale Semiconductor Preliminary State During Reset ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input On-Chip Regulator Disable — Tie this pin enable the on-chip regulator SS Tie this pin to V ...
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... Port A GPIO — These six GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, set the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA8, set bit 8 in the GPIOA_PUR register. 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... A12 23 (GPIOA4) A13 24 (GPIOA5) A14 25 (GPIOA6) A15 26 (GPIOA7) Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Address Bus — specify two of the address lines for output is external program or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control enabled register (BCR), A6– ...
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... At reset, these pins default to the EMI Data Bus function. To deactivate the internal pull-up resistor, set the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF9, set bit 9 in the GPIOF_PUR register. 56F8366 Technical Data, Rev. 7 for further information on when this Freescale Semiconductor Preliminary ...
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... D14 136 (GPIOF7) D15 137 Input/ Output (GPIOF8) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Data Bus — D14 specify part of the data for external program output is or data memory accesses. disabled, pull-up is Depending upon the state of the DRV bit in the EMI bus control ...
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... PS is tri-stated when the external bus is inactive. CS0 resets to provide the PS function as defined on the 56F80x devices. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. To deactivate the Internal pull-up resistor, clear bit 8 in the GPIOD_PUR register. 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... Output GPIOD0 48 Input/ Output (CS2) Output (CAN2_TX) Open Drain Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Data Memory Select — This signal is actually CS1 in the EMI, output is which is programmed at reset for compatibility with the 56F80x DS disabled, signal asserted low for external data memory access. ...
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... Receive Data — SCI0 receive data input pull-up enabled Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register. 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... Input TMS 122 Schmitt Input TDI 123 Schmitt Input TDO 124 Output Freescale Semiconductor Preliminary State During Reset In reset, Transmit Data — SCI1 transmit data output output is disabled, Port D GPIO — This GPIO pin can be individually programmed as pull- input or output pin. ...
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... TA1 — Timer A, Channel Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEB0. To deactivate the internal pull-up resistor, clear bit 5 of the GPIOC_PUR register. 56F8366 Technical Data, Rev. 7 Signal Description . If the SS Freescale Semiconductor Preliminary ...
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... Input/ Output SCLK0 130 Schmitt Input/ Output (GPIOE4) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Index — Quadrature Decoder 0, INDEX input pull-up enabled TA2 — Timer A, Channel 2 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin ...
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... SPI module that the current transfer received. enabled Port E GPIO — This GPIO pin can be individually programmed as input or output pin. After reset, the default state is SS0. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOE_PUR register. 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... Schmitt Input/ Output (MOSI1) Schmitt Input/ Output (GPIOC1) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. pull-up enabled TB0 — Timer B, Channel 0 SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners ...
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... In the 56F8366, the default state after reset is HOME1. In the 56F8166, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register. 56F8366 Technical Data, Rev. 7 Part 6.5.8. Part 6.5.8. Freescale Semiconductor Preliminary ...
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... PWMB0 34 Output PWMB1 35 PWMB2 36 PWMB3 39 PWMB4 40 PWMB5 41 Freescale Semiconductor Preliminary State During Signal Description Reset In reset, PWMA0 - 5 — These are six PWMA outputs. output is disabled Input, ISA0 - 2 — These three input current status pins are used for pull-up top/bottom pulse width correction in complementary channel enabled operation for PWMA ...
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... Output 0.1μF or low ESR capacitor. Analog V — Analog Reference Voltage Low. This should normally REFLO Input be connected to a low-noise V 56F8366 Technical Data, Rev. 7 Part 6.5.8. Part 6.5.8. must be less REFH — Internal pins for voltage reference . SSA Freescale Semiconductor Preliminary ...
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... Open Drain Output TC0 118 Schmitt Input/ Output (GPIOE8) Schmitt Input/ Outpu Freescale Semiconductor Preliminary State During Signal Description Reset Analog ANB0 - 3 — Analog inputs to ADC B, channel 0 Input Analog ANB4 - 7 — Analog inputs to ADC B, channel 1 Input Analog Temperature Sense Diode — This signal connects to an on-chip ...
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... To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Output Reset Output — This output reflects the internal reset state of the chip. 56F8366 Technical Data, Rev. 7 Part 6.5.6 for details. Part 6.5.6 for details. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... Signal Name Pin No. Type EXTBOOT 112 Schmitt Input EMI_MODE 143 Schmitt Input Freescale Semiconductor Preliminary State During Signal Description Reset Input, External Boot — This input is tied to V pull-up boot from off-chip memory (assuming that the on-chip Flash enabled memory is not in a secure state). Otherwise tied to ground. ...
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... Detector Figure 3-1 OCCS Block Diagram Table 10-15. A recommended crystal oscillator circuit is shown 56F8366 Technical Data, Rev. 7 Figure 3-1 shows the ZSRC SYS_CLK2 Source to SIM PLLCOD Postscaler Postscaler CLK ÷ 1,2,4,8 Bus Interface LCK Loss of Reference Clock Interrupt Freescale Semiconductor Preliminary ...
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... The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. Freescale Semiconductor Preliminary EXTAL XTAL Sample External Crystal Parameters: ...
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... COHL bit in the OSCTL register should be set External SS Clock Table Table 4-1. 56F8366 Technical Data, Rev. 7 Figure 3-4. The external clock 4-1. Flash memories’ restrictions are Freescale Semiconductor Preliminary ...
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... This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset. 2. Changing MB in software will not affect Flash memory security. Freescale Semiconductor Preliminary 56F8166 512KB Erase / Program via Flash interface unit and word writes to CDBW — ...
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... GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable in the 56F8366/56F8166). The EMI_MODE pin also affects the reset vector address, as provided in be configured as address or chip select signals to access addresses at P:$10 and above. 42 Chip Operating Mode 56F8366 Technical Data, Rev. 7 Table 4-4. Additional pins must Freescale Semiconductor Preliminary ...
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... Booting from this external address allows prototyping of the internal Boot Flash. 8. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must have its own mass erase. Freescale Semiconductor Preliminary Mode 1 2 ...
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... OnCE Transmit Register Empty 1-3 P:$16 OnCE Receive Register Full Reserved 2 P:$1C SW Interrupt 2 1 P:$1E SW Interrupt 1 0 P:$20 SW Interrupt 0 0-2 P:$22 IRQA 0-2 P:$24 IRQB Reserved 0-2 P:$28 Low-Voltage Detector (power sense) 56F8366 Technical Data, Rev Interrupt Function 2 2 Freescale Semiconductor Preliminary Part ...
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... SCI1 46 DEC1 47 DEC1 48 DEC0 49 DEC0 50 TMRD 52 TMRD 53 TMRD 54 TMRD 55 Freescale Semiconductor Preliminary Vector Base Address + 0-2 P:$2A PLL 0-2 P:$2C FM Access Error Interrupt 0-2 P:$2E FM Command Complete 0-2 P:$30 FM Command, data and address Buffers Empty Reserved 0-2 P:$34 FLEXCAN Bus Off ...
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... Reload PWM A 0-2 P:$9E PWM B Fault 0-2 P:$A0 PWM A Fault - 1 P:$A2 SW Interrupt LP 0-2 P:$A4 FlexCAN Bus Off 0-2 P:$A6 FlexCAN Error 0-2 P:$A8 FlexCAN Wake Up 0-2 P:$AA FlexCAN Message Buffer Interrupt 56F8366 Technical Data, Rev (Continued) Interrupt Function Freescale Semiconductor Preliminary ...
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... Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $03_FFF7 and $03_FFFF. Freescale Semiconductor Preliminary Table 4-6 Data Memory Map 2 ...
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... Banked Registers Unbanked Registers FM_BASE + $00 DATA_FLASH_START + $3FFF 32KB DATA_FLASH_START + $0000 Note: Data Flash is NOT available in the 56F8166 device. Sector Size Page Size 16K x 16 bits 1024 x 16 bits 1024 x 16 bits 256 x 16 bits bits 512 x 16 bits Freescale Semiconductor Preliminary ...
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... OCR (bits) X:$FF FFFC OCLSR (8 bits) X:$FF FFFD OTXRXSR (8 bits) X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFF OTX1 / ORX1 Freescale Semiconductor Preliminary Table 4-8 EOnCE Memory Map Reserved External Signal Control Register Reserved Breakpoint Unit [0] Counter Reserved Breakpoint 1 Unit [0] Mask Register ...
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... X:$00 F320 GPIOE X:$00 F330 GPIOF X:$00 F340 56F8366 Technical Data, Rev. 7 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 Freescale Semiconductor Preliminary ...
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... CSBAR 1 $1 CSBAR 2 $2 CSBAR 3 $3 CSBAR 4 $4 CSBAR 5 $5 CSBAR 6 $6 CSBAR 7 $7 CSOR 0 $8 Freescale Semiconductor Preliminary Prefix Base Address SIM X:$00 F350 LVI X:$00 F360 FM X:$00 F400 FC X:$00 F800 FC X:$00 FA00 (EMI_BASE = $00 F020) Register Description Chip Select Base Address Register 0 ...
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... Status and Control Register 56F8366 Technical Data, Rev. 7 Reset Value 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits 0x016B sets the default number of wait states to 11 for both read and write accesses Freescale Semiconductor Preliminary ...
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... TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserve $10 Compare Register 1 $11 ...
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... Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserved $10 Compare Register 1 $11 Compare Register 2 $12 Capture Register $13 Load Register $14 Hold Register $15 Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset Register Description $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register ...
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... Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register $23 Load Register $24 Hold Register $25 Counter Register $26 Control Register 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... Quad Timer D is NOT available in the 56F8166 device Register Acronym TMRD0_CMP1 TMRD0_CMP2 TMRD0_CAP TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR Freescale Semiconductor Preliminary (TMRC_BASE = $00 F0C0) Address Offset $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved ...
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... Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register $35 Counter Register 56F8366 Technical Data, Rev. 7 Register Description Freescale Semiconductor Preliminary ...
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... PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register (PWMA_BASE = $00 F140) ...
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... PWM Internal Correction Control Register (DEC0_BASE = $00 F180) Address Offset Register Description $0 Decoder Control Register $1 Filter Interval Register $2 Watchdog Time-out Register $3 Position Difference Counter Register $4 Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... DEC1_DECCR DEC1_FIR DEC1_WTR DEC1_POSD DEC1_POSDH DEC1_REV DEC1_REVH DEC1_UPOS DEC1_LPOS DEC1_UPOSH DEC1_LPOSH DEC1_UIR DEC1_LIR DEC1_IMR Freescale Semiconductor Preliminary (DEC0_BASE = $00 F180) Address Offset Register Description $7 Upper Position Counter Register $8 Lower Position Counter Register $9 Upper Position Hold Register $A Lower Position Hold Register $B Upper Initialization Register ...
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... Fast Interrupt Vector Address High 1 Register $11 IRQ Pending Register 0 $12 IRQ Pending Register 1 $13 IRQ Pending Register 2 $14 IRQ Pending Register 3 $15 IRQ Pending Register 4 $16 IRQ Pending Register 5 $1D Interrupt Control Register $1F Interrupt Priority Register 10 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $0 Control Register 1 $1 Control Register 2 $2 Zero Crossing Control Register $3 Channel List Register 1 $4 Channel List Register 2 ...
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... Channel List Register 2 $5 Sample Disable Register $6 Status Register $7 Limit Status Register $8 Zero Crossing Status Register $9 Result Register 0 $A Result Register 1 $B Result Register 2 $C Result Register 3 $D Result Register 4 $E Result Register 5 $F Result Register 6 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... ADCB_HLMT 3 ADCB_HLMT 4 ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ADCB_OFS 0 ADCB_OFS 1 ADCB_OFS 2 ADCB_OFS 3 ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ADCB_POWER ADCB_CAL Freescale Semiconductor Preliminary Address Offset Register Description $10 Result Register 7 $11 Low Limit Register 0 $12 Low Limit Register 1 $13 Low Limit Register 2 $14 Low Limit Register 3 $15 ...
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... F290) Address Offset Register Description $0 Baud Rate Register $1 Control Register Reserved $3 Status Register $4 Data Register (SPI0_BASE = $00 F2A0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register $3 Data Transmitter Register 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... Table 4-27 Computer Operating Properly Registers Address Map Register Acronym COPCTL COPTO COPCTR Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB PLLSR SHUTDOWN OSCTL Freescale Semiconductor Preliminary (SPI1_BASE = $00 F2B0) Address Offset Register Description $0 Status and Control Register $1 Data Size Register $2 Data Receive Register $3 ...
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... Reset Value 0 x 00FF 0 x 0000 0 x 0000 0 x 000F for 20-bit EMI address at reset 0000 for all other cases. See Table 4-4 for details 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 00FF — Freescale Semiconductor Preliminary ...
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... Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Freescale Semiconductor Preliminary (GPIOC_BASE = $00 F310) Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register ...
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... Reset Value 0 x FFFF 0 x 0000 0 x 0000 0 x FFFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x FFFF — Freescale Semiconductor Preliminary ...
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... SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL SIM_PCE2 Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Freescale Semiconductor Preliminary (SIM_BASE = $00 F350) Address Offset Register Description $0 Control Register $1 Reset Status Register $2 Software Control Register 0 $3 Software Control Register 1 ...
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... Information Option Register 2 Room temperature ADC reading of Temperature Sensor; value set during factory test (FC_BASE = $00 F800) Address Offset $0 Module Configuration Register Reserved $3 Control Register 0 Register $4 Control Register 1 Register $5 Free-Running Timer Register 56F8366 Technical Data, Rev. 7 Register Description Freescale Semiconductor Preliminary ...
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... FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $6 Maximum Message Buffer Configuration Register Reserved $8 Receive Global Mask High Register $9 Receive Global Mask Low Register $A Receive Buffer 14 Mask High Register ...
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... Message Buffer 4 Data Register $66 Message Buffer 4 Data Register Reserved $68 Message Buffer 5 Control / Status Register $69 Message Buffer 5 ID High Register $6A Message Buffer 5 ID Low Register $6B Message Buffer 5 Data Register $6C Message Buffer 5 Data Register $6D Message Buffer 5 Data Register 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $6E Message Buffer 5 Data Register Reserved $70 Message Buffer 6 Control / Status Register $71 Message Buffer 6 ID High Register $72 Message Buffer 6 ID Low Register ...
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... Message Buffer 12 Data Register $A4 Message Buffer 12 Data Register $A5 Message Buffer 12 Data Register $A6 Message Buffer 12 Data Register Reserved $A8 Message Buffer 13 Control / Status Register $A9 Message Buffer 13 ID High Register $AA Message Buffer 13 ID Low Register $AB Message Buffer 13 Data Register 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... FCMB15_DATA FCMB15_DATA Table 4-39 FlexCAN2 Registers Address Map FlexCAN2 is NOT available in the 56F8166 device Register Acronym FC2MCR FC2CTL0 FC2CTL1 FC2TMR FC2MAXMB Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $AC Message Buffer 13 Data Register $AD Message Buffer 13 Data Register $AE Message Buffer 13 Data Register ...
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... Message Buffer 0 Data Register Reserved $48 Message Buffer 1 Control / Status Register $49 Message Buffer 1 ID High Register $4A Message Buffer 1 ID Low Register $4B Message Buffer 1 Data Register $4C Message Buffer 1 Data Register $4D Message Buffer 1 Data Register $4E Message Buffer 1 Data Register Reserved 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
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... FC2MB4_ID_HIGH FC2MB4_ID_LOW FC2MB4_DATA FC2MB4_DATA FC2MB4_DATA FC2MB4_DATA FC2MB5_CONTROL FC2MB5_ID_HIGH FC2MB5_ID_LOW FC2MB5_DATA FC2MB5_DATA FC2MB5_DATA FC2MB5_DATA Freescale Semiconductor Preliminary (FC2_BASE = $00 FA00) Address Offset Register Description $50 Message Buffer 2 Control / Status Register $51 Message Buffer 2 ID High Register $52 Message Buffer 2 ID Low Register $53 Message Buffer 2 Data Register ...
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... Message Buffer 8 Data Register $86 Message Buffer 8 Data Register Reserved $88 Message Buffer 9 Control / Status Register $89 Message Buffer 9 ID High Register $8A Message Buffer 9 ID Low Register $8B Message Buffer 9 Data Register $8C Message Buffer 9 Data Register $8D Message Buffer 9 Data Register 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 81
... FC2MB11_DATA FC2MB11_DATA FC2MB12_CONTROL FC2MB12_ID_HIGH FC2MB12_ID_LOW FC2MB12_DATA FC2MB12_DATA FC2MB12_DATA FC2MB12_DATA FC2MB13_CONTROL FC2MB13_ID_HIGH FC2MB13_ID_LOW FC2MB13_DATA Freescale Semiconductor Preliminary (FC2_BASE = $00 FA00) Address Offset Register Description $8E Message Buffer 9 Data Register Reserved $90 Message Buffer 10 Control / Status Register $91 Message Buffer 10 ID High Register $92 Message Buffer 10 ID Low Register ...
Page 82
... Message Buffer 14 Data Register Reserved $B8 Message Buffer 15 Control / Status Register $B9 Message Buffer 15 ID High Register $BA Message Buffer 15 ID Low Register $BB Message Buffer 15 Data Register $BC Message Buffer 15 Data Register $BD Message Buffer 15 Data Register $BE Message Buffer 15 Data Register Reserved 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 83
... The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 SR[ Core status register bits indicating current interrupt mask within the core. Freescale Semiconductor Preliminary 4-5, Interrupt Vector Table Contents. 1 Permitted Exceptions SR[8] 0 Priorities ...
Page 84
... The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. 84 Current Interrupt 1 Priority Level No Interrupt or SWILP Priorities Priority 0 Priorities Priority 1 Priorities 2, 3 Priorities Priority 3 Part 5.6.30.2. 56F8366 Technical Data, Rev. 7 Required Nested Exception Priority Freescale Semiconductor Preliminary ...
Page 85
... A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. Freescale Semiconductor Preliminary any0 Level 0 82 -> ...
Page 86
... IRQ Pending Register 5 Interrupt Control Register Interrupt Priority Register 10 56F8366 Technical Data, Rev. 7 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23 5.6.30 5.6.32 Freescale Semiconductor Preliminary ...
Page 87
... W R $14 IRQP3 W R $15 IRQP4 $16 IRQP5 W Reserved R INT IPIC $1D ICTL W Reserved $1F IPR10 W = Reserved Figure 5-2 ITCN Register Map Summary Freescale Semiconductor Preliminary STPCNT IPL FMERR IPL LOCK IPL LVI IPL GPIOF FCMSGBUF IPL FCWKUP IPL IPL IPL SPI1_RCV IPL 0 SCI1_RCV SCI1_RERR IPL ...
Page 88
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1 STPCNT IPL 56F8366 Technical Data, Rev RX_REG IPL TX_REG IPL TRBUF IPL Freescale Semiconductor Preliminary ...
Page 89
... IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2) Freescale Semiconductor Preliminary FMERR IPL LOCK IPL LVI IPL 56F8366 Technical Data, Rev. 7 Register Descriptions ...
Page 90
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 90 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 91
... IRQ is priority level 1 • IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $ Read GPIOD GPIOE IPL IPL Write RESET Figure 5-6 Interrupt Priority Register 3 (IPR3) Freescale Semiconductor Preliminary GPIOF FCMSGBUF IPL FCWKUP IPL IPL 56F8366 Technical Data, Rev. 7 Register Descriptions ...
Page 92
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 92 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 93
... IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $ Read SPI0_RCV SPI1_XMIT IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) Freescale Semiconductor Preliminary SPI1_RCV IPL IPL 56F8366 Technical Data, Rev ...
Page 94
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 94 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 95
... IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SCI1_RCV SCI1_RERR ...
Page 96
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 96 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 97
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary TMRD2 IPL TMRD1 IPL ...
Page 98
... They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 98 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 99
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary TMRB2 IPL TMRB1 IPL ...
Page 100
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 100 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 101
... SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary SCI0_TIDL ...
Page 102
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 102 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 103
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary PWMA_RL PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL ...
Page 104
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 104 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 105
... The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting the full VAB to the 56800E core; see Freescale Semiconductor Preliminary 12 11 ...
Page 106
... Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $ Read Write RESET Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0) 106 FAST INTERRUPT 0 VECTOR ADDRESS LOW 56F8366 Technical Data, Rev FAST INTERRUPT FAST INTERRUPT 0 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
Page 107
... Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. Freescale Semiconductor Preliminary ...
Page 108
... This bit is reserved or not implemented read as 1 and cannot be modified by writing. 5.6.19 IRQ Pending 1 Register (IRQP1) $Base + $ Read Write RESET Figure 5-21 IRQ Pending 1 Register (IRQP1) 108 PENDING [16: PENDING [32:17 56F8366 Technical Data, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
Page 109
... IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [48:33] ...
Page 110
... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 85. • IRQ pending for this vector number • IRQ pending for this vector number 5.6.24 Reserved —Base + 17 5.6.25 Reserved —Base + 18 5.6.26 Reserved —Base + 19 5.6.27 Reserved —Base + 1A 110 PENDING [80:65 56F8366 Technical Data, Rev PENDING[81:85 Freescale Semiconductor Preliminary ...
Page 111
... Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • Normal operation (default) • All interrupts disabled Freescale Semiconductor Preliminary VAB INT_DIS ...
Page 112
... Note: This register is NOT available in the 56F8166 device. 5.6.32.1 Reserved—Bits 15–8 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 112 FLECAN2_ MSGBUF IPL 56F8366 Technical Data, Rev FLECAN2_ FLECAN2_ FLECAN2_ WKUP IPL BOFF IPL ERR IPL Freescale Semiconductor 0 0 Preliminary ...
Page 113
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 7 Register Descriptions 113 ...
Page 114
... Pull-up enables for selected peripherals • System status registers • Registers for software access to the JTAG ID of the chip • Enforcing Flash security There are discussed in more detail in the sections that follow. 114 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 115
... Wait Mode In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped. Similarly option to switch off PWM outputs to disable any motor from being driven. All other peripherals continue to run. Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 7 Features 21 clock cycles ...
Page 116
... DSP56800E Reference Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. 116 R/W R Figure 6-1 OMR 56F8366 Technical Data, Rev R/W R/W R/W R/W R Part 4.2 and Part 7 for detailed Freescale Semiconductor 0 MA R/W X Preliminary ...
Page 117
... SIM_CLKOSR Base + $B SIM_GPS Base + $C SIM_PCE Base + $D SIM_ISALH Base + $E SIM_ISALL Base + $F SIM_PCE2 Freescale Semiconductor Preliminary Table 6-1 SIM Registers (SIM_BASE = $00 F350) Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID ...
Page 118
... STOP_ MODE EBL0 RST DISABLE 0 0 SWR COPR EXTR POR CTRL JTAG 0 A21 A20 CLKDIS CLKOSEL PWM SCI1 SCI0 SPI1 SPI0 ISAL[23:22 EMI_ ONCE SW STOP_ MODE EBL RST DISABLE Freescale Semiconductor 1 0 WAIT_ DISABLE PWM CAN2 1 0 WAIT_ DISABLE 0 0 Preliminary ...
Page 119
... Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register. Base + $ Read Write RESET Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) Freescale Semiconductor Preliminary ...
Page 120
... SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3) Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality. Base + $ Read Write POR Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 120 FIELD 56F8366 Technical Data, Rev Freescale Semiconductor Preliminary 0 0 ...
Page 121
... Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Table 2-2 to identify which pins can deactivate the internal pull-up resistor. Base + $ Read 0 EMI_ PWMA1 CAN MODE Write RESET Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) Freescale Semiconductor Preliminary ...
Page 122
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.13 JTAG—Bit 3 This bit controls the pull-up resistors on the TRST, TMS and TDI pins. 122 56F8366 Technical Data, Rev. 7 pin and this bit should be SS Freescale Semiconductor Preliminary ...
Page 123
... Peripheral output function of GPIOB5 is defined to be SYS_CLK 6.5.7.5 Alternate GPIOB Peripheral Function for A20 (A20)—Bit 6 • Peripheral output function of GPIOB4 is defined to be A20 • Peripheral output function of GPIOB4 is defined to be the prescaler clock (FREF; see Freescale Semiconductor Preliminary Figure ...
Page 124
... SPI inputs/outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIOC[3: programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers. 124 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 125
... This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is used for each pin. 2. Reset configuration 3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins. Freescale Semiconductor Preliminary GPIOC_PER Register GPIO Controlled ...
Page 126
... When GPIOD[1:0] are programmed to operate as GPIOD_PER Register GPIO Controlled 0 1 SIM_ GPS Register 0 1 Control Registers 0 — 1 — — 0 EMI CSn pins are always outputs — 1 CAN2_TX is always an output CAN2_RX is always an input 56F8366 Technical Data, Rev. 7 I/O Pad Control 1 Comments Freescale Semiconductor Preliminary ...
Page 127
... This bit selects the alternate function for GPIOC2. • INDEX1/TB2 (default) • MISO1 6.5.8.6 GPIOC1 (C1)—Bit 1 This bit selects the alternate function for GPIOC1. • PHASEB1/TB1 (default) • MOSI1 6.5.8.7 GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • PHASEA1/TB0 (default) • SCLK1 Freescale Semiconductor Preliminary ...
Page 128
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.5 Decoder 1 Enable (DEC1)—Bit 11 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 128 56F8366 Technical Data, Rev SPI 1 SPI 0 PWMB Freescale Semiconductor 0 PWMA 1 Preliminary ...
Page 129
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) Freescale Semiconductor Preliminary 56F8366 Technical Data, Rev. 7 Register Descriptions 129 ...
Page 130
... Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-14 I/O Short Address Determination 130 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8366 Technical Data, Rev. 7 Instruction Portion Freescale Semiconductor Preliminary ...
Page 131
... The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a power-saving feaure. The clocks can be individually controller for each peripheral on the chip. Base + $ Read Write RESET 6.5.11.1 Reserved—Bits 15–1 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary ...
Page 132
... Typically used for power-conscious applications. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset 56F8366 Technical Data, Rev. 7 (OCCS), and the 56F8300 . Table 6-4 Description Freescale Semiconductor Preliminary ...
Page 133
... Flash security, and, finally, followed clock window in which the core is initialized. After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock. Freescale Semiconductor Preliminary D Q D-FLOP ...
Page 134
... Therefore, the security feature cannot be used unless all executing code resides on-chip. When security is enabled, any attempt to override the default internal operating mode by asserting the EXTBOOT pin in conjunction with reset will be ignored. 134 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 135
... FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. Freescale Semiconductor Preliminary Figure 7-1. FM_CLKDIV[6] will map to the 56F8366 Technical Data, Rev ...
Page 136
... Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 136 Flash Memory input clock 7 FMCLKD SYS_CLK (2) < < 200[kHz] (DIV + SYS_CLK (2)(8) < < 200[kHz] (DIV + 1) 56F8366 Technical Data, Rev. 7 DIVIDER 7 Freescale Semiconductor Preliminary ...
Page 137
... Configuration There are six GPIO ports defined on the 56F8366/56F8166. The width of each port and the associated peripheral function is shown in shown in Table 8-3. Freescale Semiconductor Preliminary 4-29 through Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is 56F8366 Technical Data, Rev ...
Page 138
... EMI Chip Selects PWMB current sense SCI0 EMI Address SPI0 TMRC N/A TMRD N/A EMI Data Reset Function EMI Address EMI Address N/A SPI1 DEC0 / TMRA GPIO EMI Chip Selects N/A SCI1 EMI Chip Selects PWMB current sense Freescale Semiconductor Preliminary ...
Page 139
... TMRD - Not available in this package 16 pins - EMI Data Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOA Freescale Semiconductor Preliminary Peripheral Function Reset GPIO Bit Function 0 Peripheral 1 Peripheral ...
Page 140
... Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 56F8366 Technical Data, Rev. 7 Functional Signal Package PIn A16 Home1 / TB3 / SS1 PHASEA0 / TA0 139 PHASEB0 / TA1 140 Index0 / TA2 141 Home0 / TA3 142 ISA0 113 ISA1 114 ISA2 115 Freescale Semiconductor Preliminary ...
Page 141
... Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8366/56F8166 Pins in italics are NOT available in the 56F8166 device GPIO Port GPIOD GPIOE Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 GPIO 1 GPIO 2 N/A 3 N/A 4 N/A 5 N/A 6 Peripheral 7 Peripheral ...
Page 142
... Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 13 Peripheral 14 Peripheral 15 Peripheral marketing representative 56F8366 Technical Data, Rev. 7 Functional Signal Package PIn D10 32 D11 133 D12 134 D13 135 D14 136 D15 137 authorized distributor Freescale Semiconductor for Preliminary ...
Page 143
... However, normal precautions are advised to avoid application maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Semiconductor Preliminary are stress ratings only, and functional operation at the maximum CAUTION of any voltages higher 56F8366 Technical Data, Rev ...
Page 144
... OUT V Pin Group STG T STG 56F8366 Technical Data, Rev. 7 Min Max Unit - 0.3 4 0.3 4 0.3 4 0.3 3.0 V -0.3 6.0 V -0.3 4.0 V -0.3 4 6.0 -0.3 6.0 V -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Freescale Semiconductor Preliminary ...
Page 145
... Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Part 12.1 for more details on thermal design considerations Junction temperature TA = Ambient temperature Freescale Semiconductor Preliminary Min 2000 200 500 Table 10-3 Thermal Characteristics ...
Page 146
... DDA DDA 2 — V +0.3 DDA -0.3 — 0.8 — — -4 — — -8 — — -12 — — 4 — — 8 — — 12 -40 — 125 -40 — 105 10,000 — — Cycle 10,000 — — Cycle 15 — — Years Freescale Semiconductor Preliminary °C ° ...
Page 147
... Input Capacitance C INC (EXTAL/XTAL) Output Capacitance C OUTC (EXTAL/XTAL) Input Capacitance C IN Output Capacitance C OUT See Pin Groups in Table 10-1 Freescale Semiconductor Preliminary Notes Min Typ 2.4 — — Pin Groups Pin Group 10 40 Pin Group 13 — Pin Group 12 — Pin Groups ...
Page 148
... ADC powered on and clocked • 60MHz Device Clock 70μA 2.5mA • All peripheral clocks are enabled • ADC powered off 56F8366 Technical Data, Rev Volts Typ Max Units 1.8 1.9 V 2.14 — V 2.7 — V μA 110 130 Test Conditions Freescale Semiconductor Preliminary ...
Page 149
... Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 950μA Stop2 100μ Output Switching Freescale Semiconductor Preliminary I I DD_ADC DD_OSC_PLL • 8MHz Device Clock 0μA 165μA • All peripheral clocks are off • ADC powered off • PLL powered off • ...
Page 150
... Unit — 2.75 V — 2.75 V — 2.75 V — 700 mA 5 μ — 30 minutes Typical Max Unit 0 0. — 200 ps — 175 ps 1 μA 100 150 Typical Max Unit 7.762 — mV/° °C 125 128 °C m 150 153 °C Freescale Semiconductor Preliminary ...
Page 151
... Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state • Data Valid state, when a signal level has reached V • Data Invalid state, when a signal level is in transition between V Freescale Semiconductor Preliminary Symbol Min V — TS0 V 3 ...
Page 152
... Symbol Min osc t 3 — rise t — fall 56F8366 Technical Data, Rev. 7 Data3 Valid Data3 Data Active Typ Max Unit μs — — — — ms — — Typ Max Unit — 120 MHz — — ns — — Freescale Semiconductor Preliminary ...
Page 153
... Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Freescale Semiconductor Preliminary t PW – Figure 10-4 External Clock Timing Table 10-14 PLL Timing ...
Page 154
... BIASL I — PD Table shows the applicable controls for each parameter and the EMI chapter of the the EMI quadrature clock is generated using both edges of the EXTAL 56F8366 Technical Data, Rev. 7 Typ Max Unit μA 80 110 μ Figure 10-5 10-16. Freescale Semiconductor Preliminary ...
Page 155
... When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Valid Data Out Hold Time after WR Deasserted Freescale Semiconductor Preliminary t ARDA WAC t WRRD ...
Page 156
... RWS 1.00 RWSS,RWS 0.00 RWSS 1.00 RWSS,RWS 0.25 + DCAEO WWSH,RWSS RWSS,RWSH 2 0. MDAR , 0.75 + DCAEO WWSS, WWSH 1.00 0.50 RWSH, WWSS, 3 MDAR 0.75 + DCAOE 1,2 Typical Unit See Figure Min Max — 10-6 16T — ns 10-6 Freescale Semiconductor Preliminary Unit ...
Page 157
... The interrupt instruction fetch is visible on the pins only in Mode 3. RESET t RAZ A0–A15, D0–D15 Figure 10-6 Asynchronous Reset Timing IRQA, IRQB Figure 10-7 External Interrupt Timing (Negative Edge-Sensitive) Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing Typical Symbol Min 3 t 63T RDA t 1 ...
Page 158
... Figure 10-10 Recovery from Stop State Using Asynchronous Interrupt Timing 158 First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O t IRI t IF 56F8366 Technical Data, Rev. 7 First Interrupt Vector Instruction Fetch First Instruction Fetch Not IRQA Interrupt Vector Freescale Semiconductor Preliminary ...
Page 159
... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary 1 Table 10-18 SPI Timing Symbol Min ELD — ELG — ...
Page 160
... SS is held High on master MSB in Bits 14– Master MSB out Bits 14– held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8366 Technical Data, Rev LSB in (ref Master LSB out LSB in (ref Master LSB out t R Freescale Semiconductor Preliminary ...
Page 161
... SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-13 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-14 SPI Slave Timing (CPHA = 1) Freescale Semiconductor Preliminary ELD Slave MSB out Bits 14– ...
Page 162
... P P OUTHL OUT Figure 10-15 Timer Timing Symbol Min 56F8366 Technical Data, Rev Max Unit See Figure — ns 10-15 — ns 10-15 — ns 10-15 — ns 10-15 P INHL P OUTHL 1, 2 Max Unit See Figure — ns 10-16 — ns 10-16 — ns 10-16 Freescale Semiconductor Preliminary ...
Page 163
... MAX 40MHz for the 56F8166 device.. 3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. RXD SCI receive data pin (Input) Freescale Semiconductor Preliminary ...
Page 164
... T 5 — WAKEUP T WAKEUP Table 10-23 JTAG Timing Symbol Min Max f DC SYS_CLK SYS_CLK — — — DH 56F8366 Technical Data, Rev Unit See Figure 1 Mbps — μs 10-19 Unit See Figure MHz 10-20 MHz 10-20 ns 10-20 ns 10-21 ns 10-21 Freescale Semiconductor Preliminary ...
Page 165
... TCK (Input – Figure 10-20 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-21 Test Access Port Timing Diagram Freescale Semiconductor Preliminary Table 10-23 JTAG Timing Symbol Min Max t — — TRST 1 ...
Page 166
... REFH — 12 +/- 2.4 +/- 3.2 LSB +/- 0.7 < +1 LSB GUARANTEED — 5 MHz — V REFH AIC — — t AIC 1 — t AIC 5 — — 3 — — 25 — +/- .004 +/- .01 +/- 27 +/- 40 Figure 10-23 — LSBs Freescale Semiconductor V Bits cycles ms 3 cycles 3 cycles μA — mV Preliminary ...
Page 167
... ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible. 6. Absolute error includes the effects of both gain error and offset error. 7. Please see the 56F8300Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 Freescale Semiconductor Preliminary Symbol Min CF1 — ...
Page 168
... S3 is closed/open. When S1/S2 are closed & open, one input of the sample and hold circuit moves REFH 168 = 0.60V and 2.70V while the other charges to the analog input voltage. When the REFH 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 169
... B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V 56800E core and standard cell logic. Freescale Semiconductor Preliminary 3 4 ...
Page 170
... LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. 170 Intercept 1.3 0.11mW / pF 1.15mW 0.11mW / pF Table 10-25 provides coefficients for calculating power dissipated 56F8366 Technical Data, Rev *F, although simulations on two Slope Freescale Semiconductor Preliminary ...
Page 171
... D10 GPIOB0 PWMB0 37 PWMB1 PWMB2 Figure 11-1 Top View, 56F8366 144-Pin LQFP Package Freescale Semiconductor Preliminary Figure 11-1 shows the package outline for the LQFP, Table 11-1 lists the pin-out for the 144-pin LQFP. 56F8366 Technical Data, Rev. 7 56F8366 Package and Pin-Out Information ...
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... XTAL PS 82 EXTAL CAP GPIOD0 84 V DD_IO 56F8366 Technical Data, Rev. 7 Pin No. Signal Name 109 ANB5 110 ANB6 111 ANB7 112 EXTBOOT 113 ISA0 114 ISA1 115 ISA2 116 TD0 117 TD1 118 TC0 3 119 V DD_IO 120 TRST Freescale Semiconductor Preliminary ...
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... A14 61 26 A15 DD_IO 32 D10 68 33 GPIOB0 69 34 PWMB0 70 35 PWMB1 71 36 PWMB2 72 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name GPIOD1 85 RSTO ISB0 86 RESET CLKMODE CAP ISB1 88 ANA0 ISB2 89 ANA1 IRQA 90 ANA2 IRQB 91 ANA3 FAULTB0 92 ANA4 FAULTB1 93 ANA5 FAULTB2 94 ANA6 ...
Page 174
... LQFP. 56F8366 Technical Data, Rev. 7 Figure 11-3 ANB4 ANB3 109 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO NC ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3 CAP EXTAL XTAL V DDA_OSC_PLL OCR_DIS Freescale Semiconductor Preliminary ...
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... CAP DD_IO A10 57 22 A11 58 23 A12 59 24 A13 60 25 A14 61 Freescale Semiconductor Preliminary Signal Name Pin No. Signal Name DD_IO PWMB3 75 D3 PWMB4 76 D4 PWMB5 77 D5 TXD1 78 D6 RXD1 79 OCR_DIS DDA_OSC_PLL RD 81 XTAL PS 82 EXTAL CAP GPIOD0 84 V DD_IO GPIOD1 85 RSTO ...
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... ANB0 V 105 ANB1 SS NC 106 ANB2 NC 107 ANB3 D2 108 ANB4 56F8366 Technical Data, Rev. 7 Pin No. Signal Name 134 D12 135 D13 136 D14 137 D15 138 A0 139 PHASEA0 140 PHASEB0 141 INDEX0 142 HOME0 143 EMI_MODE 144 V SS Freescale Semiconductor Preliminary ...
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... D1/2 D TOP VIEW H A SIDE VIEW PLATING BASE b METAL 0. SECTION A-A ° (ROTATED 90 ) 144 PLACES Figure 11-3 144-pin LQFP Mechanical Information Freescale Semiconductor Preliminary 0. TIPS 109 108 E1/2 E/2 VIEW VIEW B 0.1 A 144X θ SEATING PLANE ...
Page 178
... (Ψ where Thermocouple temperature on top of package ( T 178 , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with 56F8366 Technical Data, Rev. 7 Freescale Semiconductor Preliminary ...
Page 179
... The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs, including performance tolerances. Freescale Semiconductor Preliminary o C)/W CAUTION of any voltages ...
Page 180
... All circuitry, analog and digital, shares a common V 180 layers of the PCB with approximately 100 μF, preferably with a high-grade , V REF DDA pins. bus SS 56F8366 Technical Data, Rev. 7 and and and V pins SSA pin and cannot DDA_OSC_PLL DD_CORE Freescale Semiconductor Preliminary (GND) voltage ...
Page 181
... REFMID V REFN V REFLO V SSA_ADC Ambient Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8366VFV60 60 -40° 125° C MC56F8366MFV60 40 -40° 105° C MC56F8166VFV 60 -40° 105° C MC56F8366VFVE* 60 -40° 125° C MC56F8366MFVE* 40 -40° 105° C MC56F8166VFVE* 181 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...