MC56F8366MFVE Freescale Semiconductor, MC56F8366MFVE Datasheet - Page 107

IC DSP 16BIT 60MHZ 144-LQFP

MC56F8366MFVE

Manufacturer Part Number
MC56F8366MFVE
Description
IC DSP 16BIT 60MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8366MFVE

Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
62
Program Memory Size
544KB (272K x 16)
Program Memory Type
FLASH
Ram Size
18K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
For Use With
MC56F8367EVME - EVAL BOARD FOR MC56F83X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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5.6.14.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15
5.6.15.1
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to
5.6.16
5.6.16.1
The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
Freescale Semiconductor
Preliminary
Base + $E
Base + $F
RESET
RESET
Write
Write
Read
Read
Part
Fast Interrupt 1 Match Register (FIM1)
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Reserved—Bits 15–5
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
Reserved—Bits 15–7
Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Table
5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
15
15
0
0
0
4-5.
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
14
14
0
0
0
13
13
0
0
0
12
12
0
0
0
56F8366 Technical Data, Rev. 7
11
11
0
0
0
10
10
0
0
0
VECTOR ADDRESS LOW
9
0
0
9
0
FAST INTERRUPT 1
8
0
0
8
0
7
7
0
0
0
6
6
0
0
5
0
5
0
FAST INTERRUPT 1
4
4
0
0
3
3
0
0
2
0
2
0
Register Descriptions
1
0
1
0
0
0
0
0
107

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