MC56F8366MFVE Freescale Semiconductor, MC56F8366MFVE Datasheet - Page 128

• Manufacturer Part Number: MC56F8366MFVE
• Description: IC DSP 16BIT 60MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8366MFVE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 544KB (272K x 16)
• Program Memory Type: FLASH
• Ram Size: 18K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.9
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
6.5.9.1
Each bit controls clocks to the indicated peripheral.
6.5.9.2
Each bit controls clocks to the indicated peripheral.
6.5.9.3
Each bit controls clocks to the indicated peripheral.
6.5.9.4
Each bit controls clocks to the indicated peripheral.
6.5.9.5
Each bit controls clocks to the indicated peripheral.
128
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Base + $C
RESET
Read
Write
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
Peripheral Clock Enable Register (SIM_PCE)
External Memory Interface Enable (EMI)—Bit 15
Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Analog-to-Digital Converter A Enable (ADCA)—Bit 13
FlexCAN Enable (CAN)—Bit 12
Decoder 1 Enable (DEC1)—Bit 11
EMI
15
1
Figure 6-13 Peripheral Clock Enable Register (SIM_PCE)
ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0
14
1
13
1
12
1
11
1
56F8366 Technical Data, Rev. 7
10
1
9
1
8
1
7
1
6
1
5
1
4
1
SPI 1
3
1
Freescale Semiconductor
SPI 0
2
1
PWMB
1
1
Preliminary
PWMA
0
1