HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 919

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.2
28.2.1
Upper register: H
Lower register: L
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the converted data are
transferred to upper register H (bits 7 to 0) of the A/D data register, and the lower 2 bits are
transferred to lower register L (bits 7 and 6), for storage. Lower register L (bits 5 to 0) is always
read as 0. Table 28.3 indicates the pairings of analog input channels and A/D data registers.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 28.3 Analog Input Channels and A/D Data Registers
Group 0
reserved
reserved
AN2
AN3
Initial value:
Initial value:
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
R/W:
R/W:
Bit:
Bit:
Analog Input Channel
AD9
AD1
15
R
R
0
0
7
Group 1
AN4
AN5
AN6
AN7
AD8
AD0
14
R
R
0
6
0
AD7
13
—
R
R
0
5
0
AD6
12
—
R
R
0
4
0
Rev.6.00 Mar. 27, 2009 Page 861 of 1036
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD5
11
—
R
R
0
3
0
Section 28 A/D Converter
AD4
10
—
R
R
0
2
0
REJ09B0254-0600
AD3
—
R
R
9
0
1
0
AD2
—
R
R
8
0
0
0