HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 405

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.3.5
Setting bits A0BST (1, 0), A5BST (1, 0), and A6BST (1, 0) in BCR1 to a non-zero value allows
burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed
access to ROM that has a nibble access function. The timing for nibble access to burst ROM is
shown in figure 12.22. Two wait cycles are set. Basically, access is performed in the same way as
for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address
is changed before the next access is executed. When 8-bit ROM is connected, the number of
consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1, 0), A5BST (1, 0), or A6BST (1,
0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is
connected, only 4 can be set.
WAIT pin sampling is performed in the first access if one or more wait states are set, and is
always performed in the second and subsequent accesses.
Even if no wait state insertion is specified in burst ROM interface settings, two wait cycles are
automatically inserted in the second and subsequent accesses as shown in figure 12.23.
However, the WAIT signal is ignored in the following three cases:
•
•
•
When writing to an external address area using DMA 16-byte transfer in dual address mode
When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in single address mode
During cache write-back access
Burst ROM Interface
Rev.6.00 Mar. 27, 2009 Page 347 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600