HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 473

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Burst Mode
Once the DMAC obtains the bus right, the transfer is continued until the transfer end condition is
satisfied. However, when the DREQ pin is driven high in the external request mode with low level
detection of the DREQ pin, the bus right is passed to the other bus master after the DMA transfer
request that has already been accepted ends, even if the transfer end condition has not been
satisfied.
The burst mode cannot be used when the transfer request source is set to the serial
communications interface with FIFO (SCIF). Figure 14.15 shows a timing of the DMA transfer
operation in the burst mode.
Relationship between Request Mode and Bus Mode: Table 14.6 shows the relationship between
request mode and bus mode for each combination of DMA transfer areas.
Bus cycle
Bus cycle
DREQ
DREQ
CPU
CPU
Figure 14.14 Transfer Example in Cycle-Steal Mode
Figure 14.15 Example of Transfer in Burst Mode
CPU
CPU
CPU
CPU
DMAC DMAC DMAC
DMAC DMAC
Read
Read
Section 14 Direct Memory Access Controller (DMAC)
Bus right returned to CPU
Write
Write
Rev.6.00 Mar. 27, 2009 Page 415 of 1036
Read
CPU DMAC DMAC CPU
DMAC DMAC
Read
Write
Read
Write
DMAC
REJ09B0254-0600
Write
CPU
CPU