HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 670

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
20.2.3
This register specifies the data assignment of transmit data in each transmit frame. This register is
initialized in power on reset or software reset.
Bits 14 to 12, 5, and 4—Reserved
Bit 15—Transmit Data for Left Channel Enable (TDLE)
Bit 15: TDLE
0
1
Bits 11 to 8—Transmit Data for Left Channel Assignment (TDLA3 to TDLA0): The slot
assignment of transmit data for Left channel in transmit frame is specified from 0000(0: initial
value) to 1110(14) by this register. The transmit data for left channel is set in bits SITDL 15 to
SITDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits TDLA3 to TDLA0.
Bit 7—Transmit Data for Right Channel Enable (TDRE)
Bit 7: TDRE
0
1
Rev.6.00 Mar. 27, 2009 Page 612 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Transmit Data Assign Register (SITDAR)
Bit:
Bit:
TDRE
TDLE
R/W
R/W
15
0
7
0
Description
Disable data transmitting of left channel data
Enable data transmitting of left channel data
Description
Disable data transmitting of right channel data
Enable data transmitting of right channel data
TLREP
R/W
14
—
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
TDRA3
TDLA3
R/W
R/W
11
0
3
0
TDRA2
TDLA2
R/W
R/W
10
0
2
0
TDRA1
TDLA1
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
TDRA0
TDLA0
R/W
R/W
8
0
0
0