HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 470

MPU 3V 16K PB-FREE 240-QFP

HD6417727F100V

Manufacturer Part Number
HD6417727F100V
Description
MPU 3V 16K PB-FREE 240-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100V

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Direct Memory Access Controller (DMAC)
• Single Address Mode
The single address mode is used when transfer is performed between external devices including
external memories, one of which is accessed (selected) by the DACK signal and the other of
which is accessed by address. In this mode, the DMAC outputs the transfer request acknowledge
signal DACK to one external device, and simultaneously outputs an address to the other device;
thus DMA transfer is performed in one bus cycle. An example of transfer between an external
memory and an external device with DACK is shown in figure 14.11. The external device outputs
data to a data bus and the data is written to the external memory in a single bus cycle.
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and an external memory. In both cases, only the external request signal (DREQ) is
used as a transfer request.
Figures 14.12 and 14.13 show examples of the DMA transfer timing in single address mode.
Rev.6.00 Mar. 27, 2009 Page 412 of 1036
REJ09B0254-0600
SH7727
Data flow
Figure 14.11 Data Flow in Single Address Mode
DMAC
External address bus
DACK
DREQ
External data bus
External device
with DACK
External
memory

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