HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 30

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
20.1 Overview........................................................................................................................... 605
20.2 Register Description.......................................................................................................... 608
20.3 Operation........................................................................................................................... 630
20.4 Usage Notes ...................................................................................................................... 652
Section 21 Analog Front End Interface (AFEIF)
21.1 Overview........................................................................................................................... 657
21.2 Register Description.......................................................................................................... 660
Rev.6.00 Mar. 27, 2009 Page xxviii of lvi
REJ09B0254-0600
20.1.1 Features................................................................................................................ 605
20.1.2 Block Diagram..................................................................................................... 606
20.1.3 Terminal............................................................................................................... 607
20.1.4 Register Configuration......................................................................................... 607
20.2.1 Mode Register (SIMDR)...................................................................................... 608
20.2.2 Clock Select Register (SISCR) ............................................................................ 610
20.2.3 Transmit Data Assign Register (SITDAR) .......................................................... 612
20.2.4 Receive Data Assign Register (SIRDAR)............................................................ 613
20.2.5 Control Command Assign Register (SICDAR) ................................................... 614
20.2.6 Serial Control Register (SICTR).......................................................................... 616
20.2.7 FIFO Control Register (SIFCTR) ........................................................................ 618
20.2.8 Status Register (SISTR)....................................................................................... 620
20.2.9 Interrupt Enable Register (SIIER)........................................................................ 624
20.2.10 Transmit Data Register (SITDR) ......................................................................... 626
20.2.11 Receive Data Register (SIRDR) .......................................................................... 627
20.2.12 Transmit Control Data Register (SITCR) ............................................................ 628
20.2.13 Receive Control Data Register (SIRCR).............................................................. 629
20.3.1 Serial Clock.......................................................................................................... 630
20.3.2 Serial Timing ....................................................................................................... 631
20.3.3 Transmit Data Format .......................................................................................... 632
20.3.4 Register Assignment for Transfer Data................................................................ 634
20.3.5 Control Data Interface.......................................................................................... 637
20.3.6 FIFO..................................................................................................................... 639
20.3.7 Procedures for Transmit or Receive..................................................................... 641
20.3.8 Interrupt ............................................................................................................... 646
20.3.9 Transmit or Receive Timing ................................................................................ 648
20.4.1 Notes on Using the SIOF with Versions Previous to the SH7727B..................... 654
21.1.1 Features................................................................................................................ 657
21.1.2 Block Diagram..................................................................................................... 658
21.1.3 Pin Configuration................................................................................................. 659
21.1.4 Register Configuration......................................................................................... 659
21.2.1 AFEIF Control Register 1 and 2 (ACTR1, ACTR2) ........................................... 660
............................................................................................. 605
....................................................... 657