HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 679

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 13: TFEMP
0
1
Bit 12—Transmit Data Transfer Request (TDREQ): The transmit data transfer request is
issued when empty area of transmit FIFO exceed the setting of TFWM bit of SIFCTR register.
This bit is effective when 1 is written to TXE bit of SICTR register. This bit shows condition of
transmit FIFO. SIOF clears this bit if empty area of transmit FIFO is smaller than the set value of
TFWM bit of SIMDR register. SIOF issues a transmit interrupt if the interrupt issuing is allowed
for this bit.
Bit 12: TDREQ
0
1
Bit 10—Receive Control Data Ready (RCRDY): This bit shows condition of SIRCR register.
SIOF clears SIOF register when SIRCR register is read.
New received data will be overwritten to SIRCR register if valid data is received and written to
SIRCR register while this bit shows 1. This bit is effective when 1 is written to RXE bit of SICTR
register. SIOF issues a control interrupt if the interrupt issuing is allowed to bit.
Bit 10: RCRDY
0
1
Bit 9—Receive FIFO Full (RFFUL): This bit shows condition of Receive FIFO. SIOF clears
when SIRDR register is read. This bit is effective when 1 is written to RXE bit of SICTR register.
SIOF issues a control interrupt when the interrupt issuing is allowed.
Bit 9: RFFUL
0
1
Bit 8—Receive Data Transfer Request (RDREQ): The receive data transfer request is issued
when effective received data in receive FIFO exceed the setting of RFWM bit of SIMDR register.
This bit is effective when 1 is written to RXE bit of SICTR register. This bit shows condition of
receive FIFO. SIOF clears this bit if effective received data area in FIFO is smaller than the set
Description
Transmit FIFO is not empty
Transmit FIFO is empty
Description
No transmit request exists.
Transmit request exists.
Description
Effective data is not stored in SIRCR register
Effective data is stored in SIRCR register
Description
Receive FIFO is not full
Receive FIFO is full
Rev.6.00 Mar. 27, 2009 Page 621 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)
(Initial value)