HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 582

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
Figure 17.14 shows SCI transmission in the multiprocessor format.
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that the transmit data register (SCTDR) contains new data, and loads this data from the
SCTDR into the transmit shift register (SCTSR).
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is
transmitted in the following order from the TxD0 pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Marking: Output of 1 bits continues until the start bit of the next transmit data.
from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit,
then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit
(TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.