HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 301

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.3
9.3.1
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers are retained. The on-chip supporting
modules continue to run during sleep mode and the clock continues to be output to the CKIO and
CKIO2 pins.
In sleep mode, the STATUS1 pin is set to high and the STATUS0 pin low.
9.3.2
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module interrupt,
PINT) or reset. Interrupts are accepted during sleep mode even when the BL bit in the SR register
is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip supporting module interrupt
occurs, sleep mode is canceled and interrupt exception handling is executed. A code
corresponding to the interrupt source is set in the INTEVT and INTEVT2 registers.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
9.4
9.4.1
To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The
chip moves from the program execution state to standby mode. In standby mode, not only the
CPU, but the clock and on-chip supporting modules are halted. The clock output from the CKIO
and CKIO2 pins also halts.
The contents of the CPU and cache register are held, but some on-chip supporting modules are
initialized. Table 9.4 lists the states of registers in standby mode.
Sleep Mode
Transition to Sleep Mode
Canceling Sleep Mode
Standby Mode
Transition to Standby Mode
Section 9 Power-Down Modes and Software Reset
Rev.6.00 Mar. 27, 2009 Page 243 of 1036
REJ09B0254-0600