HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 367

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 9, 3, and 2—Area 5 OE/WE Negate Address Delay(A5TEH2, A5TEH1, and A5TEH0):
The A5TEH bits specify the OE/WE negate address delay time for the PCMCIA interface
connected area 5.
Bit 9:
A5TEH2
0
1
Bits 8, 1, and 0—Area6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, and A6TEH0):
The A6TEH bits specify the OE/WE negate address delay time for the PCMCIA interface
connected to area 6.
Bit 8:
A6TEH2
0
1
Bit 3:
A5TEH1
0
1
0
1
Bit 1:
A6TEH1
0
1
0
1
Bit 2:
A5TEH0
0
1
0
1
0
1
0
1
Bit 0:
A6TEH0
0
1
0
1
0
1
0
1
Description
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
Description
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
0.5-cycle delay
0.5-cycle delay
Rev.6.00 Mar. 27, 2009 Page 309 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600
(Initial value)
(Initial value)