HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 539

MPU 3V 16K PB-FREE 240-QFP

HD6417727F100V

Manufacturer Part Number
HD6417727F100V
Description
MPU 3V 16K PB-FREE 240-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100V

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727F100V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.1
This LSI has an on-chip serial communication interface (SCI) that supports both asynchronous and
clock synchronous serial communication. It also has a multiprocessor communication function for
serial communication among two or more processors. The SCI supports a smart card interface,
which is a serial communications feature for IC card interfaces that conforms to the ISO/IEC
standard 7816-3 for identification cards data transmission protocol type T = 0. See section 18,
Smart Card Interface, for more information.
17.1.1
Select asynchronous or clock synchronous as the serial communications mode.
• Asynchronous mode:
• Clock synchronous mode:
• Full duplex communication: The transmitting and receiving sections are independent, so the
⎯ Serial data communications are synched by start-stop in character units. The SCI can
⎯ Data length: Seven or eight bits
⎯ Stop bit length: One or two bits
⎯ Parity: Even, odd, or none
⎯ Multiprocessor bit: 1 or 0
⎯ Receive error detection: Parity, overrun, and framing errors
⎯ Break detection: By reading the RxD0 level directly from the port SC data register
⎯ Serial data communication is synchronized with a clock signal. The SCI can communicate
⎯ Data length: Eight bits
⎯ Receive error detection: Overrun errors
SCI can transmit and receive simultaneously. Both sections use double buffering, so
continuous data transfer is possible in both the transmit and receive directions.
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. It can also communicate with two or more other
processors using the multiprocessor communication function. There are 12 selectable serial
data communication formats.
(SCSPTR) when a framing error occurs
with other chips having a clock synchronous communication function. There is one serial
data communication format.
Section 17 Serial Communication Interface (SCI)
Overview
Features
Section 17 Serial Communication Interface (SCI)
Rev.6.00 Mar. 27, 2009 Page 481 of 1036
REJ09B0254-0600

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