HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 504
![MCU 3/5V 60K PB-FREE 100-QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD6473837HV
Manufacturer Part Number
HD6473837HV
Description
MCU 3/5V 60K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837HV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473837HV
Manufacturer:
ISC
Quantity:
4 500
Company:
Part Number:
HD6473837HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473837HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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TMG—Timer mode register G
Bit
Initial value
Read/Write
Note:
Timer overflow flag H
0 [Clearing condition]
1 [Setting condition]
Timer overflow flag L
0 [Clearing condition]
1 [Setting condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
When the value of TCG goes from H'FF to H'00
*
Timer overflow interrupt enable
0 TCG overflow interrupt disabled
1 TCG overflow interrupt enabled
Only a write of 0 for flag clearing is possible.
After reading OVFL = 1, cleared by writing 0 to OVFL
When the value of TCG goes from H'FF to H'00
Input capture interrupt edge select
0 Interrupts are requested at the rising edge of the input capture signal
1 Interrupts are requested at the falling edge of the input capture signal
Counter clear
0
1 0
R/(W)
OVFH
0
1
1
7
0
TCG is not cleared
TCG is cleared at the falling edge of the input capture signal
TCG is cleared at the rising edge of the input capture signal
TCG is cleared at both edges of the input capture signal
*
R/(W)
OVFL
6
0
*
OVIE
R/W
5
0
IIEGS
R/W
4
0
CCLR1
R/W
3
0
H'BC
CCLR0
Clock select
R/W
0
1 0
2
0
0
1
1
Internal clock:
Internal clock:
Internal clock:
Internal clock:
CKS1
R/W
1
0
CKS0
R/W
Timer G
0
0
/64
/32
/2
W
/2
487
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