HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 124
HD6473837HV
Manufacturer Part Number
HD6473837HV
Description
MCU 3/5V 60K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837HV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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instruction execution to interrupt exception handling completion is calculated by expression (3)
below.
Time Required before Direct Transfer from Subactive Mode to Active (Medium-Speed)
Mode: A direct transfer is made from subactive mode to active (medium-speed) mode when a
SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the
LSON bit in SYSCR1 is cleared to 0, the MSON and DTON bits in SYSCR2 are set to 1, and the
TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction
execution to interrupt exception handling completion is calculated by expression (4) below.
Direct transfer time = (number of states for SLEEP instruction execution + number of
Example: Direct transfer time for the H8/3834 Series
Direct transfer time = (number of states for SLEEP instruction execution + number of
Example: Direct transfer time for the H8/3834 Series
(when CPU clock frequency is w/8 and wait time is 8192 states)
= (2 + 1)
Notation:
tosc:
tw:
tcyc:
tsubcyc: Subclock (
(when CPU clock frequency is w/8 and wait time is 8192 states)
= (2 + 1)
Notation:
tosc:
tw:
tcyc:
tsubcyc: Subclock (
OSC clock cycle time
Watch clock cycle time
System clock ( ) cycle time
OSC clock cycle time
Watch clock cycle time
System clock ( ) cycle time
8tw + (8192 + 14)
8tw + (8192 + 14)
states for internal processing)
time designated by STS2 to STS0 bits in SCR + number of states
for interrupt exception handling execution)
states for internal processing)
designated by STS2 to STS0 bits in SCR + number of states for
interrupt exception handling execution)
SUB
SUB
) cycle time
) cycle time
2tosc = 24tw + 16412tosc
16tosc = 24tw + 131296tosc
tsubcyc before transition + (wait
tsubcyc before transition (wait time
tcyc after transition
tcyc after transition
...... (3)
...... (4)
107
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