HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 275

• Manufacturer Part Number: HD6473837HV
• Description: MCU 3/5V 60K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3
states, and containing the multiprocessor bits.
SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status
flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1.
Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified.
SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7—Transmit Data Register Empty (TDRE): Bit 7 is a status flag indicating that data has
been transferred from TDR to TSR.
Bit 7: TDRE
0
1
Bit 6—Receive Data Register Full (RDRF): Bit 6 is a status flag indicating whether there is
receive data in RDR.
Bit 6: RDRF
0
1
Note: If a receive error is detected at the end of receiving, or if bit RE in serial control register 3
258
(SCR3) is cleared to 0, RDR and RDRF are unaffected and keep their previous states. An
overrun error (OER) occurs if receiving of data is completed while bit RDRF remains set
to 1. If this happens, receive data will be lost.
Description
Indicates that transmit data written to TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
Indicates that no transmit data has been written to TDR, or the transmit data
written to TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0.
When data is transferred from TDR to TSR.
Description
Indicates there is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF.
When data is read from RDR by an instruction.
Indicates that there is receive data in RDR
Setting condition:
When receiving ends normally, with receive data transferred from RSR to RDR
(initial value)
(initial value)