HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 209

• Manufacturer Part Number: HD6473837HV
• Description: MCU 3/5V 60K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Timer Load Register C (TLC)
TLC is an 8-bit write-only register for setting the reload value of TCC.
When a reload value is set in TLC, the same value is loaded into timer counter C (TCC) as well,
and TCC starts counting up or down from that value. When TCC overflows or underflows during
operation in auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow and
underflow periods can be set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
9.4.3
Interval Timer Operation: When bit TMC7 in timer mode register C (TMC) is cleared to 0,
timer C functions as an 8-bit interval timer.
Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18. After a reset, the
counter continues uninterrupted incrementing as an interval up-counter. The clock input to timer C
is selected from seven internal clock signals output by prescalers S and W, or an external clock
input at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
Either software or hardware can control whether TCC counts up or down. The selection is made
by TMC bits TMC6 and TMC5.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If IENTC = 1
in interrupt enable register 2 (IENR2), a CPU interrupt is requested.
At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again.
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: * For details on interrupts, see 3.3, Interrupts.
192
Bit
Initial value
Read/Write
Timer Operation
TLC7
R
7
0
TLC6
R
6
0
TLC5
R
5
0
TLC4
R
4
0
TLC3
R
3
0
TLC2
R
2
0
TLC1
R
1
0
TLC0
R
0
0