HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 289
![MCU 3/5V 60K PB-FREE 100-QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD6473837HV
Manufacturer Part Number
HD6473837HV
Description
MCU 3/5V 60K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837HV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
HD6473837HV
Manufacturer:
ISC
Quantity:
4 500
Company:
Part Number:
HD6473837HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473837HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Clock
The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control
register 3 (SCR3). See table 10.14 for the settings. Either an internal clock source can be used to
run the built-in baud rate generator, or an external clock source can be input at pin SCK
When an external clock is input at pin SCK
rate.
When an internal clock source is used, SCK
the same frequency as the serial bit rate, and is synchronized as in figure 10.10 so that the rising
edge of the clock occurs in the center of each bit of transmit/receive data.
Data Transmit/Receive Operations
SCI3 Initialization: Before data is sent or received, bits TE and RE in serial control register 3
(SCR3) must be cleared to 0, after which initialization can be performed using the procedure
shown in figure 10.11.
Note: When modifying the operation mode, transfer format or other settings, always be sure to
272
Clock
Serial
data
Figure 10.10 Phase Relation of Output Clock and Communication Data in Asynchronous
clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing
RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the
receive data register (RDR).
When an external clock is used in asynchronous mode, do not stop the clock during
operation, including during initialization. When an external clock is used in synchronous
mode, do not supply the clock during initialization.
0
Mode (8-Bit Data, Parity Bit Added, and 2 Stop Bits)
D0
D1
D2
1 character (1 frame)
D3
3
3
, it should have a frequency 16 times the desired bit
is used as the clock output pin. The clock output has
D4
D5
D6
D7
0/1
1
1
3
.
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