HD6473837HV Renesas Electronics America, HD6473837HV Datasheet - Page 231

MCU 3/5V 60K PB-FREE 100-QFP

HD6473837HV

Manufacturer Part Number
HD6473837HV
Description
MCU 3/5V 60K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD6473837HV

Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Timer Bode Register G (TMG)
Note: * Only 0 can be written, to clear flag.
TMG is an 8-bit read/write register. It controls the choice of four input clocks, counter clear
selection, and edge selection for input capture interrupt requests. It also indicates overflow status
and enables or disables overflow interrupt requests.
Upon reset, TMG is initialized to H'00.
Bit 7—Timer Overflow Flag H (OVFH): Bit 7 is a status flag indicating that TCG overflowed
(from H'FF to H'00) when the input capture signal was high. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 7: OVFH
0
1
Bit 6—Timer Overflow Flag L (OVFL): Bit 6 is a status flag indicating that TCG overflowed
(from H'FF to H'00) when the input capture signal was low, or in interval timer operation. This
flag is set by hardware and cleared by software. It cannot be set by software.
Bit 6: OVFL
0
1
Bit 5—Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables TCG overflow
interrupts.
Bit 5: OVIE
0
1
214
Bit
Initial value
Read/Write
OVFH
R/W*
Description
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting conditions:
Set when the value of TCG overflows from H'FF to H'00
Description
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting conditions:
Set when the value of TCG overflows from H'FF to H'00
Description
TCG overflow interrupt disabled
TCG overflow interrupt enabled
7
0
OVFL
R/W*
6
0
OVIE
R/W
5
0
IIEGS
R/W
4
0
CCLR1
R/W
3
0
CCLR0
R/W
2
0
CKS1
R/W
1
0
(initial value)
(initial value)
(initial value)
CKS0
R/W
0
0

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