DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 851

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
4
3
2
Bit Name
NACKF
STOP
AL
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
No acknowledge detection flag
[Setting condition]
•
[Clearing condition]
•
Stop condition detection flag
[Setting condition]
•
•
[Clearing condition]
•
Arbitration Lost Flag
This flag indicates that arbitration was lost in master
mode.
When two or more master devices attempt to seize
the bus at nearly the same time, if the I
interface detects data differing from the data it sent, it
sets AL to 1 to indicate that the bus has been taken
by another master.
[Setting conditions]
•
•
[Clearing condition]
•
When no acknowledge is detected from the
receive device in transmission while the ACKE bit
in ICIER is 1
When 0 is written in NACKF after reading NACKF
= 1
In master mode, when a stop condition is detected
after frame transfer
In slave mode, when a stop condition is detected
after the general call address or the first byte
slave address, next to detection of start condition,
accords with the address set in SAR
When 0 is written in STOP after reading STOP = 1
If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode
When the internal SDA high in master mode while
a start condition is detected
When 0 is written in AL/OVE after reading
AL/OVE=1
Section 16 I
Rev.7.00 Mar. 18, 2009 page 783 of 1136
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700
2
C bus