DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 771

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
Bit Name
TDRE
RDRF
Serial Status Register (SSR)
Initial Value
1
0
R/W
R/(W) *
R/(W) *
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the next
data is completed while the RDRF flag is set to 1,
an overrun error occurs and receive data will be
lost.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR, and
data writing to TDR is enabled.
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
When serial reception ends normally and
receive data is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF
= 1
When the DMAC or DTC is activated by an RXI
interrupt and transferred data from RDR
Rev.7.00 Mar. 18, 2009 page 703 of 1136
REJ09B0109-0700