DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 307

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit
timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O
port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected to the external address space and DRAM data is to be retained
in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR.
Software Standby: When a transition is made to normal software standby, the PALL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.
DQMU, DQML
Precharge-sel
Address bus
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
SDRAM
Data bus
CKE
RAS
CAS
WE
φ
φ
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Software
standby
NOP
T
Rc2
T
Rp1
T
Rp2
Column address
Rev.7.00 Mar. 18, 2009 page 239 of 1136
PALL
T
p
Continuous synchronous DRAM space write
Row address
Row address
ACTV
Section 6 Bus Controller (BSC)
T
r
T
NOP
c1
REJ09B0109-0700
Column address
NOP
T
cl
NOP
T
c2