MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 465

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.7
The MCF5272 uses line read transfers to access 16 bytes to support cache line filling DMA transfers, and
MOVEM instructions, when appropriate. A cache line read accesses a block of four longwords, aligned to
a longword memory boundary, by supplying a starting address that points to one of the longwords and
incrementing A[3:0] of the supplied address for each transfer. A longword read accesses a single longword
aligned to a longword boundary and increments A1 and A0 if the accessed port size is smaller than 32 bits.
A word read accesses a single word of data, aligned to a word boundary and increments A0 if the accessed
port size is smaller than 16 bits.
The MCF5272 uses line write transfers to access a 16-byte operand for MOVEM instructions and DMA
transfers, when appropriate. A line write accesses a block of four longwords, aligned to a longword
memory boundary, by supplying a starting address that points to one of the longwords and increments
A[3:0] of the supplied address for each transfer. A longword write accesses a single longword aligned to
a longword boundary and increments A1 and A0 if the accessed port size is smaller than 32 bits. A word
write accesses a single word of data, aligned to a word boundary and increments A0 if the accessed port
size is smaller than 16 bits.
The MCF5272 hardware supports the following types of burst transfers.
Freescale Semiconductor
•
SDCLK
A[22:0]
D[31:0]
OE
R/W
CSn
BS[3:0]
TA
Sixteen byte cache line read bursts from 32-bit wide SDRAM with access times of n-1-1-1. The
value of n depends on read, write, page miss, page hit, etc. See
Burst Data Transfers
(H)
(H)
Figure 20-17. Longword Write with Address Setup and Address Hold;
MCF5272 ColdFire
C1
EBI = 11; 32-Bit Port, Internal Termination
®
Integrated Microprocessor User’s Manual, Rev. 3
C2
C3
C4
Chapter 9, “SDRAM
Controller,”
Bus Operation
20-17