MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 127

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4.3
The address breakpoint low and high registers (ABLR, ABHR),
processor’s data address space that can be used as part of the trigger. These register values are compared
with the address for each transfer on the processor’s high-speed local bus. The trigger definition register
(TDR) identifies the trigger as one of three cases:
Table 5-6
Table 5-7
Freescale Semiconductor
31–0
31–0
Bits
Bits
1. identically the value in ABLR
2. inside the range bound by ABLR and ABHR inclusive
3. outside that same range
DRc[4–0]
Reset
Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Field
Address
R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG
Name
Name
describes ABLR fields.
describes ABHR fields.
Address Breakpoint Registers (ABLR, ABHR)
instruction and via the BDM port using the
ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and
via the BDM port using the
31
Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
Breakpoints for specific addresses are programmed into ABLR.
MCF5272 ColdFire
Figure 5-6. Address Breakpoint Registers (ABLR, ABHR)
WDMREG
Table 5-7. ABHR Field Description
Table 5-6. ABLR Field Description
®
Integrated Microprocessor User’s Manual, Rev. 3
command.
0x0D (ABLR); 0x0C (ABHR)
RDMREG
Address
Description
and
Description
—
WDMREG
Figure
commands.
5-6, define regions in the
Debug Support
0
5-9