MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 109

• Manufacturer Part Number: MCF5272VM66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, UART, Ethernet, SPI, USB, QSPI
• Maximum Clock Frequency: 166 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.4 V to 1.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5
The features of the instruction cache are as follows:
4.5.1
The instruction cache,
containing 16 bytes. Memory consists of a 64-entry tag array (containing addresses and a valid bit) and a
1-Kbyte instruction data array, organized as 64 x 128 bits.
The two memory arrays are accessed in parallel: bits 9–4 of the instruction fetch address provide the index
into the tag array; bits 9–2 address the data array. The tag array outputs the address mapped to the given
cache location along with the valid bit for the line. This address field is compared to bits 31–10 of the
instruction fetch address from the local bus to determine if a cache hit in the memory array has occurred.
If the desired address is mapped into the cache memory, the output of the data array is driven onto the
ColdFire core's local data bus completing the access in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded
into the instruction cache.
The instruction cache also contains a 16-byte fill buffer that provides temporary storage for the last line
fetched in response to a cache miss. With each instruction fetch, the contents of the line-fill buffer are
examined. Thus, each instruction fetch address examines both the tag memory array and the line-fill buffer
to see if the desired address is mapped into either hardware resource. A cache hit in either the memory
array or the line-fill buffer is serviced in a single cycle. Because the line-fill buffer maintains valid bits on
a longword basis, hits in the buffer can be serviced immediately without waiting for the entire line to be
fetched.
If the referenced address is not contained in the memory array or the line-fill buffer, the instruction cache
initiates the required external fetch operation. In most situations, this is a 16-byte line-sized burst
reference.
Hardware is nonblocking, meaning the ColdFire core's local bus is released after the initial access of a
miss. Thus, the cache, SRAM, or ROM module can service subsequent requests while the rest of the line
is being fetched and loaded into the fill buffer.
Generally, longword references are used for sequential fetches. If the processor branches to an odd word
address, a word-sized fetch is generated. The memory array of the instruction cache is enabled only if
CACR[CENB] is asserted.
Freescale Semiconductor
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1-Kbyte direct-mapped cache
Single-cycle access on cache hits
Physically located on ColdFire core's high-speed local bus
Nonblocking design to maximize performance
16-byte line-fill buffer
Configurable cache miss-fetch algorithm
Instruction Cache Overview
Instruction Cache Physical Organization
MCF5272 ColdFire
Figure
4-3, is a direct-mapped single-cycle memory, organized as 64 lines, each
®
Integrated Microprocessor User’s Manual, Rev. 3
Local Memory
4-7