MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 288
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Universal Serial Bus (USB)
12.3.4
The access times for the USB module depend on whether the access is to a register, to an endpoint FIFO
(EPnDR register), or to the configuration RAM.
12.3.4.1
The USB module registers are accessed through the internal S-bus. Each register access takes 3 clock
cycles for reads and writes.
12.3.4.2
The FIFO access time depends on the size, the time between accesses, and whether the previous FIFO
access was for the same endpoint. After a longword access to an endpoint’s FIFO, the next longword in
the FIFO is cached for a quicker access time on the next longword read. This mechanism is reset every
time another endpoint is accessed.
12.3.4.3
The configuration RAM is longword accessible only. Access times for reads from the configuration RAM
are eight clock cycles per access. Clock cycle access times for back-to-back writes to the configuration
RAM are 3-5-5-5-5-5... Access times for writes separated by at least 1 clock cycle are 3-3-3-3-3-3…
12-30
9. Interface #0 Descriptor
10. Endpoint #1 Descriptor
11. Configuration #3 Descriptor
12. Interface #0 Descriptor
13. Endpoint #1 Descriptor
14. Endpoint #2 Descriptor
USB Module Access Times
Registers
Endpoint FIFOs
Configuration RAM
Byte
Word
Long (back to back)
Long (1 clock gap)
Long (2 clock gap)
Long (3+ clock gap)
MCF5272 ColdFire
Access Type
Table 12-19. USB FIFO Access Timing
Table 12-19
®
Integrated Microprocessor User’s Manual, Rev. 3
5
6
8-4-6-6-6-6...
8-3-5-5-5-5...
8-3-4-4-4-4...
8-3-3-3-3-3...
shows the access times for the FIFOs.
Read
4
4
4-6-6-6-6-6...
4-5-5-5-5-5...
4-4-4-4-4-4...
4-4-4-4-4-4...
Write
Freescale Semiconductor
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