MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 348
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Queued Serial Peripheral Interface (QSPI) Module
Figure 14-4
14-10
13–10
Bits
7–0
9
8
QSPI_Dout
QSPI_CLK
QSPI_Din
QSPI_CS
CPHA
Name
CPOL
BAUD
BITS
shows an example of a QSPI clocking and data transfer.
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Transfer size. Determines the number of bits to be transferred for each entry in the queue.
Value Bits per transfer
0000 16
0001– 0111 Reserved
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
Clock polarity. Defines the clock polarity of SCK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.
Baud rate divider. The baud rate is selected by writing 0, or a value in the range 2–255. 1 is not a valid
value. A value of zero disables the QSPI. The desired QSPI_CLK baud rate is related to CLKIN and
QMR[BAUD] by the following expression:
msb
15
15
QMR[BAUD] = SystemClock / [2 × (desired QSPI_CLK baud rate)]
MCF5272 ColdFire
A
14
14
Figure 14-4. QSPI Clocking and Data Transfer Example
Table 14-3. QMR Field Descriptions (continued)
13
13
12
12
11
11
®
Integrated Microprocessor User’s Manual, Rev. 3
10
10
9
9
8
8
Description
7
7
6
6
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
5
5
4
4
3
3
2
2
1
1
Freescale Semiconductor
0
0
B
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