MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 186
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Chip Select Module
8.1.3
CS0 is enabled after reset and is used to access boot ROM. The memory port width of CS0 is defined by
the state of QSPI_CLK/BUSW1 and QSPI_CS0/BUSW0. These two bits should be configured to define
the width of the boot ROM connected to CS0, as described in
Configuration
8.2
Each chip select is controlled through two 32-bit registers. The chip select base registers (CSBR0–CSBR7)
are used to enable the chip select and to configure the base address, port size, bus interface type, and
address space. The chip select option registers (CSOR0–CSOR7) are used to configure the address mask,
additional setup/hold, extended burst capability, wait states, and read/write access.
8-2
Chip Select Registers
Boot CS0 Operation
Pins.”
1
+ 0x04C CSOR1 CS option register 1
+ 0x05C CSOR3 CS option register 3
+ 0x06C CSOR5 CS option register 5
+ 0x07C CSOR7 CS option register 7
+ 0x040
+ 0x044
+ 0x048
+ 0x050
+ 0x054
+ 0x058
+ 0x060
+ 0x064
+ 0x068
+ 0x070
+ 0x074
+ 0x078
Offset
The nibble shown as x resets as 00xx, where the undefined bits represent the
BW field. QSPI_CS0/BUSW0 and QSPI_CLK/BUSW1 program the bus width
for CS0 at reset
MCF5272 ColdFire
CSOR0 CS option register 0
CSOR2 CS option register 2
CSOR4 CS option register 4
CSOR6 CS option register 6
CSBR0 CS base register 0
CSBR1 CS base register 1
CSBR2 CS base register 2
CSBR3 CS base register 3
CSBR4 CS base register 4
CSBR5 CS base register 5
CSBR6 CS base register 6
CSBR7 CS base register 7
Name
Table 8-1. CSCR and CSOR Values after Reset
®
Integrated Microprocessor User’s Manual, Rev. 3
Chip Select Register
Section 19.18, “Operating Mode
0x0000_0x01
0xFFFF_F078
0xFFFF_F078
0xFFFF_F078
0xFFFF_F078
0xFFFF_F078
0xFFFF_F078
0xFFFF_F078
0xFFFF_F078
0x0000_1300
0x0000_2300
0x0000_3300
0x0000_4300
0x0000_5300
0x0000_6300
0x0000_7700
Reset
1
Freescale Semiconductor
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