MCF5272VM66J Freescale Semiconductor, MCF5272VM66J Datasheet - Page 117
MCF5272VM66J
Manufacturer Part Number
MCF5272VM66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets
1.MCF5272CVF66J.pdf
(544 pages)
2.MCF5272CVF66J.pdf
(12 pages)
3.MCF5272VM66J.pdf
(44 pages)
Specifications of MCF5272VM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, UART, Ethernet, SPI, USB, QSPI
Maximum Clock Frequency
166 MHz
Number Of Timers
4
Operating Supply Voltage
1.4 V to 1.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Freescale Semiconductor
Bits
4–3
1–0
6
5
2
Name
BWE
CM
WP
—
—
Cache mode. Defines whether the memory access is cacheable or noncacheable.
0 Caching enabled
1 Caching disabled
Buffered write enable. Generally, the enabling of buffered writes provides higher system performance but
recovery from access errors may be more difficult. For the ColdFire CPU, reporting access errors on operand
writes is always imprecise; enabling buffered writes further decouples the write instruction from the signaling
of the fault.
0 Termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle
1 A write cycle on the local bus is terminated immediately and the operation is then buffered in the bus
Reserved, should be cleared.
Write protect. Selects the write privilege of the memory region.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
is completed.
controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus
and the external bus.
MCF5272 ColdFire
Table 4-9. ACRn Field Descriptions (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Local Memory
4-15
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