DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 603

• Manufacturer Part Number: DF2160BVTE10
• Description: IC H8S MCU FLASH 64K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2160BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2160BVTE10; HD64F2160BVTE10

Note:
Bit
0
Bit
7
6
5
4
3
2
STR2
Bit Name Initial Value Slave Host Description
OBF1
Bit Name Initial Value Slave Host Description
DBU27
DBU26
DBU25
DBU24
C/D2
DBU22
* Only 0 can be written to clear the flag.
0
0
0
0
0
0
0
R/(W) * R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
Defined by User
The user can use this bit as necessary.
Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 547 of 788
REJ09B0300-0300